| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Implement module item reduction properly | Yann Herklotz | 2019-05-11 | 1 | -6/+6 |
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| * | Fix warnings for CI | Yann Herklotz | 2019-05-11 | 1 | -2/+1 |
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| * | Add new reduction techniques | Yann Herklotz | 2019-05-11 | 1 | -32/+139 |
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| * | Add parser and reducer tests | Yann Herklotz | 2019-05-09 | 1 | -0/+50 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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