verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Bump version to v0.6.0.2v0.6.0.2	Yann Herklotz	2019-12-26	1	-2/+2
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*	Bump version to v0.6.0.1v0.6.0.1	Yann Herklotz	2019-12-26	1	-2/+2
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*	Bump to version 0.6.0.0v0.6.0.0	Yann Herklotz	2019-12-25	1	-2/+2
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*	Upgrade version to v0.5.0.0v0.5.0.0	Yann Herklotz	2019-11-24	1	-2/+2
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*	Support proper Quartus Pro version	Yann Herklotz	2019-11-14	1	-0/+1
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*	Add reduction for simulation failures	Yann Herklotz	2019-11-12	1	-2/+2
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*	Add counter example parsing	Yann Herklotz	2019-11-10	1	-0/+1
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*	Add data-file installation path	Yann Herklotz	2019-10-29	1	-2/+2
\| \| \| \| \|	This removes the need to recursively copy the data directory which will also save on space.
*	Add mtl dependency to enable easier use of transformers	Yann Herklotz	2019-10-27	1	-30/+30
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*	Update the version string for future release	Yann Herklotz	2019-10-25	1	-1/+1
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*	Rename Sim to Tool	Yann Herklotz	2019-10-18	1	-9/+9
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*	Remove reference to nix files	Yann Herklotz	2019-10-07	1	-1/+0
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*	Fix cabal filev0.4.0.0	Yann Herklotz	2019-10-06	1	-1/+10
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*	[Fix #63] Make build pass again	Yann Herklotz	2019-10-06	1	-4/+3
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*	Rename main modules	Yann Herklotz	2019-09-18	1	-35/+35
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*	Small changes to .cabal	Yann Herklotz	2019-09-06	1	-2/+7
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*	Rename cabal file to fix nix	Yann Herklotz	2019-09-04	1	-0/+155