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# VeriFuzz [](https://travis-ci.com/ymherklotz/verifuzz)
Verilog Fuzzer to test the major verilog compilers by generating random, valid
verilog.
It currently supports the following simulators:
- [Yosys](http://www.clifford.at/yosys/)
- [Icarus Verilog](http://iverilog.icarus.com)
- [Xst](https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_using_xst_for_synthesis.htm)
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