blob: 12e48e4cdc29530f70cbb34e59171e3456492b10 (
plain)
1
2
3
4
5
6
7
8
9
10
|
# VeriFuzz ![Build Status](https://travis-ci.com/ymherklotz/verifuzz.svg?token=qfBKKGwxeWkjDsy7e16x&branch=master)
Verilog Fuzzer to test the major verilog compilers by generating random, valid
verilog.
It currently supports the following simulators:
- [Yosys](http://www.clifford.at/yosys/)
- [Icarus Verilog](http://iverilog.icarus.com)
- [Xst](https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_using_xst_for_synthesis.htm)
|