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Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
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path:
root
/
app
/
Main.hs
blob: 7160b5d608cbe14e40c3bb4bc7b11aad289f38cf (
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module
Main
where
import
VeriFuzz main :: IO
()
main
=
defaultMain