| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | Main.hs | 1316 | logstatsplain |
| -rw-r--r-- | Simulation.hs | 4109 | logstatsplain |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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