1_minimal.v « vivado « bugs - verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

about summary refs log tree commit diff stats

path: root/bugs/vivado/1_minimal.v

blob: 59cec6c88fa838c123007f4cb0e4c76a15d27638 (plain)

(* use_dsp48="no" *) module top
   (y, wire0);
   output wire y;
   input wire      wire0;
   wire [1:0]       wire4;
   assign wire4 = 1'b1;
   assign y = (wire4 <<< 1'h1) && wire0;
endmodule