| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | 1_generated.v | 1046 | logstatsplain |
| -rw-r--r-- | 1_minimal.v | 193 | logstatsplain |
| -rw-r--r-- | 1_original.v | 16639 | logstatsplain |
| -rw-r--r-- | 2_minimal.v | 1175 | logstatsplain |
| -rw-r--r-- | 2_original.v | 2738 | logstatsplain |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
| aboutsummaryrefslogtreecommitdiffstats |