index
:
verismith
dev/distance
dev/reducer
develop
feature/hashmap
feature/ignored-constructs
feature/nondeterminism
feature/update-dependencies
fix/remove-DRBG
master
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
examples
/
config.toml
blob: b340afec48f86faed8e3a074802169d75c51c2be (
plain
)
1
2
3
4
[probability]
assign
=
5
always
=
1