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:
verismith
dev/distance
dev/reducer
develop
feature/hashmap
feature/ignored-constructs
feature/nondeterminism
feature/update-dependencies
fix/remove-DRBG
master
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
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examples
Mode
Name
Size
-rw-r--r--
config.toml
824
log
stats
plain
-rw-r--r--
decl.v
557
log
stats
plain
-rw-r--r--
shift.v
2289
log
stats
plain
-rw-r--r--
simple.v
391
log
stats
plain