aboutsummaryrefslogtreecommitdiffstats
path: root/src/Main.hs
blob: 0d49a3c454f9b275ac99effc5cb1e1ffabdb6694 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
module Main where

import Data.Bits
import Test.QuickCheck hiding ((.&.), (.|.))

type Input = Bool

data Gate = And
          | Or
          | Xor
          | Nand
          | Nor
          deriving (Show)

data Circuit a = In a
               | Node Gate (Circuit a) (Circuit a)
               deriving (Show)

instance Arbitrary Gate where
  arbitrary = elements [And, Or, Xor, Nand, Nor]

instance (Arbitrary a) => Arbitrary (Circuit a) where
  arbitrary = do
    x <- arbitrary
    frequency [(1, return (In x)), (1, arbNode)]
      where
        arbNode = Node <$> arbitrary <*> arbitrary <*> arbitrary

eval :: (Bits a) => Circuit a -> a
eval (In val) = val
eval (Node And c1 c2) = eval c1 .&. eval c2
eval (Node Or c1 c2) = eval c1 .|. eval c2
eval (Node Xor c1 c2) = eval c1 `xor` eval c2
eval (Node Nand c1 c2) = complement $ eval c1 .&. eval c2
eval (Node Nor c1 c2) = complement $ eval c1 .|. eval c2

main :: IO ()
main = sample (arbitrary :: Gen (Circuit Input))