index
:
verismith
dev/distance
dev/reducer
develop
feature/hashmap
feature/ignored-constructs
feature/nondeterminism
feature/update-dependencies
fix/remove-DRBG
master
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
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Test
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VeriFuzz
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Graph
Mode
Name
Size
-rw-r--r--
ASTGen.hs
2444
log
stats
plain
-rw-r--r--
CodeGen.hs
1862
log
stats
plain
-rw-r--r--
Random.hs
1581
log
stats
plain