| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | Circuit.hs | 960 | logstatsplain |
| -rw-r--r-- | CodeGen.hs | 6839 | logstatsplain |
| d--------- | Graph | 112 | logstatsplain |
| -rw-r--r-- | Helpers.hs | 2067 | logstatsplain |
| d--------- | Internal | 71 | logstatsplain |
| -rw-r--r-- | Mutate.hs | 2732 | logstatsplain |
| -rw-r--r-- | VerilogAST.hs | 13128 | logstatsplain |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
| aboutsummaryrefslogtreecommitdiffstats |