index
:
verismith
dev/distance
dev/reducer
develop
feature/hashmap
feature/ignored-constructs
feature/nondeterminism
feature/update-dependencies
fix/remove-DRBG
master
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
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path:
root
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src
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VeriFuzz
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Circuit
Mode
Name
Size
-rw-r--r--
ASTGen.hs
2638
log
stats
plain
-rw-r--r--
CodeGen.hs
1828
log
stats
plain
-rw-r--r--
Random.hs
1985
log
stats
plain
-rw-r--r--
RandomAlt.hs
849
log
stats
plain