index
:
verismith
dev/distance
dev/reducer
develop
feature/hashmap
feature/ignored-constructs
feature/nondeterminism
feature/update-dependencies
fix/remove-DRBG
master
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
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path:
root
/
src
/
VeriFuzz
/
Internal
Mode
Name
Size
-rw-r--r--
AST.hs
2117
log
stats
plain
-rw-r--r--
Circuit.hs
1032
log
stats
plain
-rw-r--r--
Simulator.hs
3335
log
stats
plain
-rw-r--r--
Template.hs
2782
log
stats
plain