| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | AST.hs | 2117 | logstatsplain |
| -rw-r--r-- | Circuit.hs | 1032 | logstatsplain |
| -rw-r--r-- | Simulator.hs | 3335 | logstatsplain |
| -rw-r--r-- | Template.hs | 2782 | logstatsplain |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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