blob: 99b102cf1ca2c49bb1ec7af1188adbdff36e4e70 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
|
{-|
Module : VeriFuzz.Sim.Vivado
Description : Vivado Synthesiser implementation.
Copyright : (c) 2019, Yann Herklotz Grave
License : GPL-3
Maintainer : ymherklotz [at] gmail [dot] com
Stability : experimental
Portability : POSIX
Vivado Synthesiser implementation.
-}
module VeriFuzz.Sim.Vivado
( Vivado(..)
, defaultVivado
)
where
import Prelude hiding (FilePath)
import Shelly
import VeriFuzz.Sim.Internal
import VeriFuzz.Sim.Template
import VeriFuzz.Verilog.CodeGen
newtype Vivado = Vivado { vivadoPath :: FilePath }
deriving (Eq, Show)
instance Tool Vivado where
toText _ = "vivado"
instance Synthesiser Vivado where
runSynth = runSynthVivado
defaultVivado :: Vivado
defaultVivado = Vivado "vivado"
runSynthVivado :: Vivado -> SourceInfo -> FilePath -> Sh ()
runSynthVivado sim (SourceInfo top src) outf = do
dir <- pwd
writefile vivadoTcl . vivadoSynthConfig top $ toTextIgnore outf
writefile "rtl.v" $ genSource src
run_ "sed" ["s/^module/(* use_dsp48=\"no\" *) module/;", "-i", "rtl.v"]
echoP "Vivado: run"
logger_ dir "vivado"
$ timeout
(vivadoPath sim)
["-mode", "batch", "-source", toTextIgnore vivadoTcl]
echoP "Vivado: done"
where vivadoTcl = fromText ("vivado_" <> top) <.> "tcl"
|