| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | Env.hs | 1589 | logstatsplain |
| -rw-r--r-- | Icarus.hs | 3574 | logstatsplain |
| -rw-r--r-- | Internal.hs | 3887 | logstatsplain |
| -rw-r--r-- | Reduce.hs | 5326 | logstatsplain |
| -rw-r--r-- | Template.hs | 3172 | logstatsplain |
| -rw-r--r-- | Vivado.hs | 1385 | logstatsplain |
| -rw-r--r-- | XST.hs | 1804 | logstatsplain |
| -rw-r--r-- | Yosys.hs | 2906 | logstatsplain |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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