blob: 415a45e7738709227e6e24b225e777e30504b32e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
{-|
Module : VeriFuzz.Simulator.Xst
Description : Xst (ise) simulator implementation.
Copyright : (c) 2018-2019, Yann Herklotz Grave
License : BSD-3
Maintainer : ymherklotz [at] gmail [dot] com
Stability : experimental
Portability : POSIX
Xst (ise) simulator implementation.
-}
{-# LANGUAGE QuasiQuotes #-}
module VeriFuzz.Simulator.Xst where
import Control.Lens hiding ((<.>))
import Prelude hiding (FilePath)
import Shelly
import Text.Shakespeare.Text (st)
import VeriFuzz.Simulator.General
import VeriFuzz.Simulator.Internal.Template
import VeriFuzz.Verilog
import VeriFuzz.Verilog
data Xst = Xst { xstPath :: FilePath
, netgenPath :: FilePath
}
instance Simulator Xst where
toText _ = "xst"
instance Synthesize Xst where
runSynth = runSynthXst
defaultXst :: Xst
defaultXst =
Xst "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xst" "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/netgen"
runSynthXst :: Xst -> ModDecl -> FilePath -> Sh ()
runSynthXst sim m outf = do
writefile xstFile $ xstSynthConfig m
writefile prjFile [st|verilog work "rtl.v"|]
writefile "rtl.v" $ genSource m
timeout_ (xstPath sim) ["-ifn", toTextIgnore xstFile]
run_ (netgenPath sim)
["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf]
run_ "sed" ["-i", "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;", toTextIgnore outf]
where
modFile = fromText $ modName m
xstFile = modFile <.> "xst"
prjFile = modFile <.> "prj"
|
