| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | AST.hs | 15762 | logstatsplain |
| -rw-r--r-- | CodeGen.hs | 9276 | logstatsplain |
| -rw-r--r-- | Helpers.hs | 1921 | logstatsplain |
| -rw-r--r-- | Mutate.hs | 6219 | logstatsplain |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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