1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
|
{-|
Module : Reduce
Description : Test reduction.
Copyright : (c) 2019, Yann Herklotz Grave
License : GPL-3
Maintainer : ymherklotz [at] gmail [dot] com
Stability : experimental
Portability : POSIX
Test reduction.
-}
{-# LANGUAGE QuasiQuotes #-}
module Reduce
(reduceUnitTests)
where
import Data.List ((\\))
import Test.Tasty
import Test.Tasty.HUnit
import VeriFuzz
import VeriFuzz.Reduce
import VeriFuzz.Verilog.Quote
reduceUnitTests :: TestTree
reduceUnitTests = testGroup "Reducer tests"
[ moduleReducerTest
, modItemReduceTest
, activeWireTest
]
activeWireTest :: TestTree
activeWireTest = testCase "Active wires" $ do
findActiveWires verilog1 \\ ["x", "y", "z", "w"] @?= []
findActiveWires verilog2 \\ ["x", "y", "z"] @?= []
where
verilog1 = head $ getVerilog [verilog|
module top(y, x);
input x;
output y;
wire z;
wire w;
assign z = 0;
assign w = 2;
assign y = w + z;
endmodule
|]
verilog2 = head $ getVerilog [verilog|
module top(y, x);
input x;
output y;
wire z;
wire w;
assign z = 0;
endmodule
|]
modItemReduceTest :: TestTree
modItemReduceTest = testCase "Module items" $ do
halveModItems srcInfo1 @?= golden1
where
srcInfo1 = SourceInfo "top" [verilog|
module top(y, x);
input x;
output y;
wire z;
wire w;
assign z = x;
assign w = z;
assign y = w;
endmodule
|]
golden1 = Dual (SourceInfo "top" [verilog|
module top(y, x);
input x;
output y;
wire z;
wire w;
assign z = x;
assign y = w;
endmodule
|]) $ SourceInfo "top" [verilog|
module top(y, x);
input x;
output y;
wire z;
wire w;
assign w = 1'b0;
assign y = w;
endmodule
|]
moduleReducerTest :: TestTree
moduleReducerTest = testCase "Module reducer" $ do
halveModules srcInfo1 @?= golden1
halveModules srcInfo2 @?= golden2
where
srcInfo1 = SourceInfo "top" [verilog|
module top(y, x);
output wire [4:0] y;
input wire [4:0] x;
m m(y, x);
endmodule
module m(y, x);
output wire [4:0] y;
input wire [4:0] x;
endmodule
|]
golden1 = Single $ SourceInfo "top" [verilog|
module top(y, x);
output wire [4:0] y;
input wire [4:0] x;
endmodule
|]
srcInfo2 = SourceInfo "top" [verilog|
module top(y, x);
output wire [4:0] y;
input wire [4:0] x;
m m(y, x);
m2 m2(y, x);
endmodule
module m(y, x);
output wire [4:0] y;
input wire [4:0] x;
endmodule
module m2(y, x);
output wire [4:0] y;
input wire [4:0] x;
endmodule
|]
golden2 = Dual (SourceInfo "top" [verilog|
module top(y, x);
output wire [4:0] y;
input wire [4:0] x;
m m(y, x);
endmodule
module m(y, x);
output wire [4:0] y;
input wire [4:0] x;
endmodule
|]) $ SourceInfo "top" [verilog|
module top(y, x);
output wire [4:0] y;
input wire [4:0] x;
m2 m2(y, x);
endmodule
module m2(y, x);
output wire [4:0] y;
input wire [4:0] x;
endmodule
|]
|