index
:
verismith
dev/distance
dev/reducer
develop
feature/hashmap
feature/ignored-constructs
feature/nondeterminism
feature/update-dependencies
fix/remove-DRBG
master
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
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test
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Name
Size
-rw-r--r--
Doctest.hs
316
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stats
plain
-rw-r--r--
Property.hs
2289
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plain
-rw-r--r--
Test.hs
207
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plain
-rw-r--r--
Unit.hs
2492
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plain
-rw-r--r--
doctest.json
102
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plain