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Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
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tests
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Doctest.hs
blob: 736ea721391685132dde2db9d9b49c96f4b5eaf7 (
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{-# options_ghc -F -pgmF doctest-discover -optF test/doctest.json #-}