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:
verismith
dev/distance
dev/reducer
develop
feature/hashmap
feature/ignored-constructs
feature/nondeterminism
feature/update-dependencies
fix/remove-DRBG
master
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
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tests
Mode
Name
Size
-rw-r--r--
Property.hs
584
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stats
plain
-rw-r--r--
Test.hs
193
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plain
-rw-r--r--
Unit.hs
351
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plain