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| author | m8pple <dt10@imperial.ac.uk> | 2015-10-20 12:11:51 +0100 |
|---|---|---|
| committer | m8pple <dt10@imperial.ac.uk> | 2015-10-20 12:11:51 +0100 |
| commit | 8142f166a04ecb103ed503e9c78d862cdbce7678 (patch) | |
| tree | cf3c1ba93f7b79b6ae564c3f50c13564d95c8c6f | |
| parent | 3dfc42de7a4c6605313abbfc276f8539e39a6422 (diff) | |
| download | MipsCPU-8142f166a04ecb103ed503e9c78d862cdbce7678.tar.gz MipsCPU-8142f166a04ecb103ed503e9c78d862cdbce7678.zip | |
Added JALR to sg_instructionsArray. Closes #7.
| -rw-r--r-- | src/shared/mips_test_framework.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/shared/mips_test_framework.cpp b/src/shared/mips_test_framework.cpp index 77de0ad..61eb695 100644 --- a/src/shared/mips_test_framework.cpp +++ b/src/shared/mips_test_framework.cpp @@ -52,6 +52,7 @@ static const instr_info_t sg_instructionsArray[]= {"DIVU","Divide unsigned"}, {"J","Jump"}, {"JAL","Jump and link"}, + {"JALR","Jump and link register"}, {"JR","Jump register"}, {"LB","Load byte"}, {"LBU","Load byte unsigned"}, |