adding all initial files

10 files changed, 315 insertions, 1 deletions

diff --git a/makefile b/makefile
index 2f38cb0..2fbdf61 100644
--- a/makefile
+++ b/makefile
@@ -1,6 +1,6 @@
 # Your login. For example, mine is dt10. Yours
 # won't be eie2ugs...
-LOGIN ?= eie2ugs
+LOGIN ?= ymh15
 
 # Turn on all warnings
 CPPFLAGS += -W -Wall
diff --git a/src/shared/mips_mem_ram.o b/src/shared/mips_mem_ram.o
new file mode 100644
index 0000000..718d8dc
--- /dev/null
+++ b/src/shared/mips_mem_ram.o
diff --git a/src/shared/mips_test_framework.o b/src/shared/mips_test_framework.o
new file mode 100644
index 0000000..9790ca3
--- /dev/null
+++ b/src/shared/mips_test_framework.o
diff --git a/src/ymh15/mips_cpu.cpp b/src/ymh15/mips_cpu.cpp
new file mode 100644
index 0000000..49e8cff
--- /dev/null
+++ b/src/ymh15/mips_cpu.cpp
@@ -0,0 +1,176 @@
+#include "../../include/mips.h"
+#include "mips_cpu_ymh15.hpp"
+
+struct mips_cpu_impl {
+    mips_mem_h mem;
+    uint32_t regs[32];
+    uint32_t pc;
+    uint32_t overflow;
+};
+
+mips_cpu_h mips_cpu_create(mips_mem_h mem) {
+    mips_cpu_impl* new_mips_cpu = new mips_cpu_impl;
+    
+    new_mips_cpu->mem = mem;
+    new_mips_cpu->pc = 0;
+    new_mips_cpu->overflow = 0;
+    
+    for(int i = 0; i < 32; ++i) {
+        new_mips_cpu->regs[i] = 0;
+    }
+
+    return new_mips_cpu;
+}
+
+mips_error mips_cpu_reset(mips_cpu_h state) {
+    if(!state) {
+        return mips_ErrorInvalidArgument;
+    }
+    
+    state->pc = 0;
+    state->overflow = 0;
+
+    for(int i = 0; i < 32; ++i) {
+        state->regs[i] = 0;
+    }
+
+    return mips_Success;
+}
+
+mips_error mips_cpu_get_register(mips_cpu_h state, unsigned index,
+                                 uint32_t *value) {
+    if(!state || !value) {
+        return mips_ErrorInvalidArgument;
+    }
+    
+    *value = state->regs[index];
+    
+    return mips_Success;
+}
+
+mips_error mips_cpu_set_register(mips_cpu_h state, unsigned index,
+                                 uint32_t value) {
+    if(!state) {
+        return mips_ErrorInvalidArgument;
+    }
+    
+    state->regs[index] = value;
+    
+    return mips_Success;
+}
+
+
+mips_error mips_cpu_set_pc(mips_cpu_h state, uint32_t pc) {
+    if(!state) {
+        return mips_ErrorInvalidArgument;
+    }
+    
+    state->pc = pc;
+
+    return mips_Success;
+}
+
+mips_error mips_cpu_get_pc(mips_cpu_h state, uint32_t *pc) {
+    if(!state || !pc) {
+        return mips_ErrorInvalidArgument;
+    }
+    
+    *pc = state->pc;
+
+    return mips_Success;
+}
+
+mips_error mips_cpu_step(mips_cpu_h state) {
+    if(!state) {
+        return mips_ErrorInvalidArgument;
+    }
+
+    read_instruction(state);
+    
+    state->pc += 4;
+
+    return mips_Success;
+}
+
+mips_error mips_cpu_set_debug_level(mips_cpu_h state, unsigned level,
+                                    FILE *dest) {
+    if(!state || !dest) {
+        return mips_ErrorInvalidArgument;
+    }
+    
+    //TODO
+    
+    return mips_Success;
+}
+
+void mips_cpu_free(mips_cpu_h state) {
+    if(state) {
+        delete state;
+    }
+}
+
+mips_error read_instruction(mips_cpu_h state) {
+    uint32_t inst;
+    mips_mem_read(state->mem, state->pc, 4, (uint8_t*)&inst);
+    
+    exec_instruction(state, inst);
+
+    return mips_Success;
+}
+
+mips_error exec_instruction(mips_cpu_h state, uint32_t inst) {
+    uint32_t var[8];
+    for(int i = 0; i < 8; ++i) {
+        var[i] = 0;
+    }
+    
+    if(((inst >> 26)&0x3f) == 0) {
+        // R Type
+        var[REG_S] = inst >> 21;
+        var[REG_T] = (inst >> 16)&0x1f;
+        var[REG_D] = (inst >> 11)&0x1f;
+        var[SHIFT] = (inst >> 6)&0x1f;
+        var[FUNC] = inst&0x3f;
+        
+        exec_R(state, var);
+    } else if(((inst >> 26)&0x3f) < 4) {
+        var[OPCODE] = inst >> 26;
+        var[REG_S] = (inst >> 21)&0x1f;
+        var[REG_D] = (inst >> 16)&0x1f;
+        var[IMM] = inst&0xffff;
+        
+        exec_J(state, var);
+    } else {
+        var[OPCODE] = inst >> 26;
+        var[MEM] = inst&0x3ffffff;
+        
+        exec_I(state, var);
+    }
+
+    return mips_Success;
+}
+
+void exec_R(mips_cpu_h state, uint32_t var[8]) {
+    if((var[FUNC]&0xf0) == 0x20 && (var[FUNC]&0xf) < 4) {
+        add_sub(state, var);
+    }
+}
+
+void exec_J(mips_cpu_h state, uint32_t var[8]) {
+    //TODO
+}
+
+void exec_I(mips_cpu_h state, uint32_t var[8]) {
+    //TODO
+}
+
+void add_sub(mips_cpu_h state, uint32_t var[8]) {
+    if((var[FUNC]&0xf) < 2) {
+        state->regs[var[REG_D]] = state->regs[var[REG_S]] +
+            state->regs[var[REG_T]];
+        state->overflow = 0;
+        if((var[FUNC]&0xf) == 0) {
+            state->overflow = 1;
+        }
+    }
+}
diff --git a/src/ymh15/mips_cpu.o b/src/ymh15/mips_cpu.o
new file mode 100644
index 0000000..403a250
--- /dev/null
+++ b/src/ymh15/mips_cpu.o
diff --git a/src/ymh15/mips_cpu_ymh15.hpp b/src/ymh15/mips_cpu_ymh15.hpp
new file mode 100644
index 0000000..fea8c2f
--- /dev/null
+++ b/src/ymh15/mips_cpu_ymh15.hpp
@@ -0,0 +1,22 @@
+#ifndef MIPS_CPU_YMH15_H
+#define MIPS_CPU_YMH15_H
+
+#include "../../include/mips.h"
+
+#define OPCODE 0
+#define REG_S 1
+#define REG_T 2
+#define REG_D 3
+#define SHIFT 4
+#define FUNC 5
+#define IMM 6
+#define MEM 7
+
+mips_error read_instruction(mips_cpu_h state);
+mips_error exec_instruction(mips_cpu_h state, uint32_t inst);
+void exec_R(mips_cpu_h state, uint32_t var[8]);
+void exec_J(mips_cpu_h state, uint32_t var[8]);
+void exec_I(mips_cpu_h state, uint32_t var[8]);
+void add_sub(mips_cpu_h state, uint32_t var[8]);
+
+#endif // MIPS_CPU_YMH15_H
diff --git a/src/ymh15/test_mips b/src/ymh15/test_mips
new file mode 100755
index 0000000..40b7762
--- /dev/null
+++ b/src/ymh15/test_mips
diff --git a/src/ymh15/test_mips.cpp b/src/ymh15/test_mips.cpp
new file mode 100644
index 0000000..3523844
--- /dev/null
+++ b/src/ymh15/test_mips.cpp
@@ -0,0 +1,101 @@
+#include "../../include/mips.h"
+#include "test_mips_ymh15.hpp"
+
+#include <iostream>
+
+using namespace std;
+
+int main() {
+    mips_mem_h ram = mips_mem_create_ram(4096);
+    mips_cpu_h cpu = mips_cpu_create(ram);
+    
+    uint32_t inst = gen_instruction(9, 10, 8, 0, 0x21);
+    uint32_t inst2 = gen_instruction(12, 13, 11, 0, 0x20);
+    uint32_t ans;
+    uint32_t ans2;
+    
+    mips_mem_write(ram, 0, 4, (uint8_t*)&inst);
+    mips_mem_write(ram, 4, 4, (uint8_t*)&inst2);
+
+    mips_cpu_set_register(cpu, 9, 4);
+    mips_cpu_set_register(cpu, 10, 5);
+    mips_cpu_set_register(cpu, 12, 232);
+    mips_cpu_set_register(cpu, 13, 2356);
+    
+    mips_cpu_step(cpu);
+    mips_cpu_step(cpu);
+    
+    mips_cpu_get_register(cpu, 8, &ans);
+    mips_cpu_get_register(cpu, 11, &ans2);
+    
+    if(!ans || !ans2) {
+        printf("failed\n");
+    } else {
+        printf("4 + 5 = %d\n", ans);
+        printf("232 + 2356 = %d\n", ans2);
+    }
+    return 0;
+}
+
+// R Type
+uint32_t gen_instruction(uint32_t src1, uint32_t src2, uint32_t dest,
+                     uint32_t shift, uint32_t function) {
+    uint32_t inst = 0;
+    inst = inst | src1 << 21 | src2 << 16 | dest << 11 | shift << 6 |
+        function;
+    return inst;
+}
+
+// I Type
+uint32_t gen_instruction(uint32_t opcode, uint32_t src, uint32_t dest,
+                     uint32_t Astart) {
+    uint32_t inst = 0;
+    inst = inst | opcode << 26 | src << 21 | dest << 16 | Astart;
+    return inst;
+}
+
+// J Type
+uint32_t gen_instruction(uint32_t opcode, uint32_t memory) {
+    uint32_t inst = 0;
+    inst = inst | opcode << 26 | memory;
+    return inst;
+}
+
+uint32_t change_endianness(uint32_t inst) {
+    inst = (inst << 24 | ((inst << 8)&0x00ff0000) |
+            ((inst >> 8)&0x0000ff00) |inst >> 24);
+    return inst;
+}
+
+void test_endian(mips_mem_h ram) {
+    uint32_t address, length, data, data0, data1, data2, data3, dataf;
+    address = 0;
+    length = 4;
+    data = 0x01234567;
+    data0 = 0;
+    data1 = 0;
+    data2 = 0;
+    data3 = 0;
+    dataf = 0;
+
+    printf("Data in: %#010x\n", data);
+
+    //data = (data << 24 | ((data << 8)&0x00ff0000) |
+    //        ((data >> 8)&0x0000ff00) |data >> 24);
+
+    mips_mem_write(ram, address, length, (uint8_t*)&data);
+    mips_mem_read(ram, address, 1, (uint8_t*)&data0);
+    mips_mem_read(ram, address+1, 1, (uint8_t*)&data1);
+    mips_mem_read(ram, address+2, 1, (uint8_t*)&data2);
+    mips_mem_read(ram, address+3, 1, (uint8_t*)&data3);
+
+    mips_mem_read(ram, address, 4, (uint8_t*)&dataf);
+    
+    cout << "Data at " << address << ": " << data0 << endl;
+    cout << "Data at " << address+1 << ": " << data1 << endl;
+    cout << "Data at " << address+2 << ": " << data2 << endl;
+    cout << "Data at " << address+3 << ": " << data3 << endl;
+
+    printf("Dataf: %#010x\n", dataf);
+}
+
diff --git a/src/ymh15/test_mips.o b/src/ymh15/test_mips.o
new file mode 100644
index 0000000..a095d53
--- /dev/null
+++ b/src/ymh15/test_mips.o
diff --git a/src/ymh15/test_mips_ymh15.hpp b/src/ymh15/test_mips_ymh15.hpp
new file mode 100644
index 0000000..98c9789
--- /dev/null
+++ b/src/ymh15/test_mips_ymh15.hpp
@@ -0,0 +1,15 @@
+#ifndef TEST_MIPS_YMH15_H
+#define TEST_MIPS_YMH15_H
+
+#include "../../include/mips.h"
+
+uint32_t gen_instruction(uint32_t src1, uint32_t src2, uint32_t dest,
+                         uint32_t shift, uint32_t function);
+uint32_t gen_instruction(uint32_t opcode, uint32_t src, uint32_t dest,
+                         uint32_t Astart);
+uint32_t gen_instruction(uint32_t opcode, uint32_t memory);
+uint32_t change_endianness(uint32_t inst);
+
+void test_endian(mips_mem_h ram);
+
+#endif // TEST_MIPS_YMH15_H