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| author | zedarider <ymherklotz@gmail.com> | 2016-10-27 18:53:16 +0100 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-10-27 18:53:16 +0100 |
| commit | 72b51899b0d71a43af81c89a5eeeedb08c2b6d0b (patch) | |
| tree | 46828b93573164544da8058cf2b8789bd7d7fa66 /src/ymh15/mips_cpu_ymh15.hpp | |
| parent | 58e3d34252d003f748b73d55b81155a5f76c0a54 (diff) | |
| download | MipsCPU-72b51899b0d71a43af81c89a5eeeedb08c2b6d0b.tar.gz MipsCPU-72b51899b0d71a43af81c89a5eeeedb08c2b6d0b.zip | |
Finished cpu completely except some corner cases
Diffstat (limited to 'src/ymh15/mips_cpu_ymh15.hpp')
| -rw-r--r-- | src/ymh15/mips_cpu_ymh15.hpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/ymh15/mips_cpu_ymh15.hpp b/src/ymh15/mips_cpu_ymh15.hpp index 085c59c..05f21f9 100644 --- a/src/ymh15/mips_cpu_ymh15.hpp +++ b/src/ymh15/mips_cpu_ymh15.hpp @@ -16,6 +16,7 @@ #define MEM 7 // Functions +#define NOOP 0x0 #define SLL 0x0 #define SRL 0x2 #define SRA 0x3 @@ -89,5 +90,6 @@ mips_error store(mips_cpu_h state, uint32_t var[8]); mips_error move(mips_cpu_h state, uint32_t var[8]); mips_error mult_div(mips_cpu_h state, uint32_t var[8]); mips_error shift(mips_cpu_h state, uint32_t var[8]); +mips_error set(mips_cpu_h state, uint32_t var[8], uint32_t imm); #endif // MIPS_CPU_YMH15_H |