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-rw-r--r--src/ymh15/test_mips_ymh15.hpp28
1 files changed, 13 insertions, 15 deletions
diff --git a/src/ymh15/test_mips_ymh15.hpp b/src/ymh15/test_mips_ymh15.hpp
index ca9f9fe..bd360f1 100644
--- a/src/ymh15/test_mips_ymh15.hpp
+++ b/src/ymh15/test_mips_ymh15.hpp
@@ -63,21 +63,19 @@
#define SH 0x29
#define SW 0x2b
-uint32_t gen_instruction(uint32_t src1, uint32_t src2, uint32_t dest,
- uint32_t shift, uint32_t function);
-uint32_t gen_instruction(uint32_t opcode, uint32_t src, uint32_t dest,
- uint32_t Astart);
+uint32_t gen_instruction(uint32_t src1, uint32_t src2, uint32_t dest, uint32_t shift, uint32_t function);
+uint32_t gen_instruction(uint32_t opcode, uint32_t src, uint32_t dest, uint32_t Astart);
uint32_t gen_instruction(uint32_t opcode, uint32_t memory);
-uint32_t change_endianness(uint32_t inst);
-int test_add(mips_mem_h ram, mips_cpu_h cpu, uint32_t type, uint32_t max,
- uint8_t value, unsigned i_t);
-int test_bitwise(mips_mem_h ram, mips_cpu_h cpu, uint8_t op);
-int test_I(mips_mem_h ram, mips_cpu_h cpu, uint32_t type, uint32_t num1,
- uint32_t num2);
-int test_branch(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t a, uint8_t l, uint32_t opc2, uint32_t b);
-int test_jump(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode);
-int test_load(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t word);
-int test_mult_div(mips_mem_h ram, mips_cpu_h cpu, uint32_t opcode, uint32_t num1, uint32_t num2);
+void change_endianness(uint32_t &inst);
-#endif // TEST_MIPS_YMH15_H
+int check_reg(mips_cpu_h state, uint8_t reg_addr, uint32_t check_value);
+int check_error(mips_error err, mips_error expected_err);
+
+mips_error set_instruction(mips_mem_h mem, mips_cpu_h state, uint32_t mem_location, uint32_t src1, uint32_t src2, uint32_t dest, uint32_t shift, uint32_t function);
+mips_error set_instruction(mips_mem_h mem, mips_cpu_h state, uint32_t mem_location, uint32_t opcode, uint32_t src, uint32_t dest, uint32_t Astart);
+mips_error set_instruction(mips_mem_h mem, mips_cpu_h state, uint32_t mem_location, uint32_t opcode, uint32_t memory);
+
+mips_error rand_reg(mips_cpu_h state);
+
+#endif