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MipsCPU
master
Cycle accurate MIPS CPU simulation.
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Age
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*
Finished cpu completely except some corner cases
zedarider
2016-10-27
12
-572
/
+1971
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Merge branch 'master' of https://github.com/m8pple/arch2-2016-cw
zedarider
2016-10-27
1
-3
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+3
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\
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*
Added brackets for peace of mind
George Punter
2016-10-25
1
-1
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+1
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*
Fixed subtle bug and changed comment about max RAM size
George Punter
2016-10-25
1
-2
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+2
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*
Allow 512MB ram at request of @lorenzo2897. Closes #42.
m8pple
2016-10-24
1
-1
/
+1
*
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nearly finished
zedarider
2016-10-27
8
-37
/
+412
*
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adding more instructions to the test cases and the cpu
zedarider
2016-10-25
8
-75
/
+520
*
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cleaned up
zedarider
2016-10-17
3
-5
/
+5
*
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added bitwise operators
zedarider
2016-10-17
7
-13
/
+90
*
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fully working add and sub
zedarider
2016-10-17
7
-80
/
+108
*
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adding all initial files
zedarider
2016-10-14
9
-0
/
+314
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/
*
Updated for 2016.
David Thomas
2016-10-10
3
-267
/
+11
*
Modified description of LH and LHU. Thanks to @roastedpork. Closes #8.
m8pple
2015-10-22
1
-2
/
+2
*
Added JALR to sg_instructionsArray. Closes #7.
m8pple
2015-10-20
1
-0
/
+1
*
Converted %lf to %f in relation to issue #5.
m8pple
2015-10-19
1
-4
/
+4
*
Adding example eie2ugs code from live tutorial + recorded tutorial:
m8pple
2015-10-19
2
-0
/
+259
*
Update for 2015.
m8pple
2015-10-12
3
-132
/
+5
*
Fix for issue #15
OJFord
2014-10-23
1
-1
/
+1
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Very basic skeleton from the classes.
m8pple
2014-10-20
2
-0
/
+132
*
Initial push.
m8pple
2014-10-16
2
-0
/
+346