Add LED examplemain

4 files changed, 175 insertions, 0 deletions

diff --git a/blink/ButterStick_r1.0.pcf b/blink/ButterStick_r1.0.pcf
new file mode 100644
index 0000000..07cbfbc
--- /dev/null
+++ b/blink/ButterStick_r1.0.pcf
@@ -0,0 +1,38 @@
+# This is a partial constraints file for ButterStick r1.0,
+# produced based on
+# https://github.com/butterstick-fpga/butterstick-bootloader/blob/main/gateware/rtl/platform/butterstick_r1d0.py
+# All mistakes mine, Tommy Thorn, 2021
+
+LOCATE COMP "clk30" SITE "B12";
+IOBUF PORT "clk30" IO_TYPE=LVCMOS18;
+FREQUENCY PORT "clk30" 30.0 MHz;
+
+LOCATE COMP "rst_n" SITE "R3";
+IOBUF PORT "rst_n" IO_TYPE=LVCMOS33 OPENDRAIN=ON;
+
+LOCATE COMP "user_btn[0]" SITE "U16";
+IOBUF PORT "user_btn[0]" IO_TYPE=SSTL135_I;
+
+LOCATE COMP "user_btn[1]" SITE "T17";
+IOBUF PORT "user_btn[1]" IO_TYPE=SSTL135_I;
+
+LOCATE COMP "led_rgb_multiplex_a[0]" SITE "C13";
+IOBUF PORT "led_rgb_multiplex_a[0]" IO_TYPE=LVCMOS33;
+LOCATE COMP "led_rgb_multiplex_a[1]" SITE "D12";
+IOBUF PORT "led_rgb_multiplex_a[1]" IO_TYPE=LVCMOS33;
+LOCATE COMP "led_rgb_multiplex_a[2]" SITE "U2";
+IOBUF PORT "led_rgb_multiplex_a[2]" IO_TYPE=LVCMOS33;
+LOCATE COMP "led_rgb_multiplex_a[3]" SITE "T3";
+IOBUF PORT "led_rgb_multiplex_a[3]" IO_TYPE=LVCMOS33;
+LOCATE COMP "led_rgb_multiplex_a[4]" SITE "D13";
+IOBUF PORT "led_rgb_multiplex_a[4]" IO_TYPE=LVCMOS33;
+LOCATE COMP "led_rgb_multiplex_a[5]" SITE "E13";
+IOBUF PORT "led_rgb_multiplex_a[5]" IO_TYPE=LVCMOS33;
+LOCATE COMP "led_rgb_multiplex_a[6]" SITE "C16";
+IOBUF PORT "led_rgb_multiplex_a[6]" IO_TYPE=LVCMOS33;
+LOCATE COMP "led_rgb_multiplex_b[0]" SITE "T1";
+IOBUF PORT "led_rgb_multiplex_b[0]" IO_TYPE=LVCMOS33;
+LOCATE COMP "led_rgb_multiplex_b[1]" SITE "R1";
+IOBUF PORT "led_rgb_multiplex_b[1]" IO_TYPE=LVCMOS33;
+LOCATE COMP "led_rgb_multiplex_b[2]" SITE "U1";
+IOBUF PORT "led_rgb_multiplex_b[2]" IO_TYPE=LVCMOS33;
diff --git a/blink/Makefile b/blink/Makefile
new file mode 100644
index 0000000..ad38b9b
--- /dev/null
+++ b/blink/Makefile
@@ -0,0 +1,43 @@
+PROJ=blink
+
+# Add Windows and Unix support
+RM         = rm -rf
+COPY       = cp -a
+PATH_SEP   = /
+ifeq ($(OS),Windows_NT)
+# When SHELL=sh.exe and this actually exists, make will silently
+# switch to using that instead of cmd.exe.  Unfortunately, there's
+# no way to tell which environment we're running under without either
+# (1) printing out an error message, or (2) finding something that
+# works everywhere.
+# As a result, we force the shell to be cmd.exe, so it works both
+# under cygwin and normal Windows.
+SHELL      = cmd.exe
+COPY       = copy
+RM         = del
+PATH_SEP   = \\
+endif
+
+
+all: ${PROJ}.dfu
+
+dfu: ${PROJ}.dfu
+	dfu-util --alt 0 --download $< --reset
+
+%.json: %.v
+	yosys -p "read_verilog $<; synth_ecp5 -json $@"
+
+%_out.config: %.json
+	nextpnr-ecp5 --json $< --textcfg $@ --um5g-85k --speed 8 --package CABGA381 --lpf ButterStick_r1.0.pcf
+
+%.bit: %_out.config
+	ecppack --compress --freq 38.8 --input $< --bit $@
+
+%.dfu : %.bit
+	$(COPY) $< $@
+	dfu-suffix -v 1209 -p 5af1 -a $@
+
+clean:
+	$(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu
+
+.PHONY: prog clean
diff --git a/blink/README.md b/blink/README.md
new file mode 100644
index 0000000..7ce57e8
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+++ b/blink/README.md
@@ -0,0 +1,68 @@
+# Blink
+
+## Overview
+
+`blink` is the hello world of any development board: Make the LED
+blink!  A singular Verilog file describes a module that increments a
+32-bit counter.  That counter increments on every positive clock
+edge. It uses the top 10 bits to drive the 3 color selectors and the 7
+LED enablers.  You'll see <something>.
+
+## Usage
+
+Be sure the bootloader is active (indicated by a alternating blue and
+green wave on the 7 LEDs which spread from the middle out).  If it
+isn't, then unplug the board, hold down button 0 *while* replugging
+the board, then release buttom 0.
+
+At this point
+
+```
+$ make dfu
+```
+
+should compile and program the blinky design resulting in a counter
+pattern being display, cycling though black, red, blue, red, green,
+green, and cyan before advancing the counter.  (Note, this is a
+simplistic example and the current limiting is on the common anode of
+the LED, so lower Vforward of RED will dominate the current.  This is
+better addressed by multiplexing the colors.)
+
+
+If this doesn't, check
+
+ * (Linux only) that `/etc/udev/rules.d/10-butterstick-dfu.rules` exist and contains
+   `ATTRS{idVendor}=="1209", ATTRS{idProduct}=="5af1", MODE="0666", GROUP="plugdev", TAG+="uaccess"`
+
+ * That the USB cable is actually perfect (I had a marginal cable that almost worked ...)
+
+ * That the ButterStick is connected to the machine that runs the DFU command.
+
+## Files
+
+- `blink.v` — The `top` (e.g. 'main') module, that describes the
+  counter, and the hooking of the counter's bits to the RGB LEDs.
+
+- `Makefile` — The make build script that will produce the bitstream
+  from the HDL. It makes uses of the open source tools `yosys`,
+  `nextpnr`, `ecppack`, and `dfu-util` to go from hardware description
+  to bitstream to running on the FPGA.
+
+## Concepts Introduced
+
+- Simple toolchain flow via Makefile
+- Introduction to Verilog HDL.
+- Registers and assignment, always blocks, sequential logic.
+- Wire assignment (combinitorial logic)
+
+### Further Reading
+
+- [fpga4fun: Counters 1 - Binary
+  counters](https://www.fpga4fun.com/Counters1.html) — A more in detph
+  look at how the counting is done like in this example.
+
+- [fpga4fun: HDL
+  Tutorials](https://www.fpga4fun.com/HDLtutorials.html) — Take a look
+  at the Verilog section, as all of these examples use Verilog. VHDL,
+  is another hardware description language that isn't used in these
+  examples.
diff --git a/blink/blink.v b/blink/blink.v
new file mode 100644
index 0000000..535d819
--- /dev/null
+++ b/blink/blink.v
@@ -0,0 +1,26 @@
+/* Copyright 2020 Gregory Davill <greg.davill@gmail.com>
+   Hacked 2021 by Tommy Thorn
+*/
+`default_nettype none
+
+/*
+ *  Blink an LED on the ButterStick r1.0 using Verilog
+ */
+
+module top (
+    input clk30,
+    output [6:0] led_rgb_multiplex_a,
+    output [2:0] led_rgb_multiplex_b
+);
+    // Create a 32 bit register
+    reg [31:0] counter = 0;
+
+    // Every positive edge increment register by 1
+    always @(posedge clk30) begin
+        counter <= counter + 1;
+    end
+
+    // Output inverted values of counter onto LEDs
+    assign led_rgb_multiplex_b = counter[26:24];
+    assign led_rgb_multiplex_a = counter[31:25];
+endmodule