Remaining ctl insts except Pbuiltin (maps to error)

1 files changed, 45 insertions, 31 deletions

diff --git a/aarch64/PostpassSchedulingOracle.ml b/aarch64/PostpassSchedulingOracle.ml
index 79a95df9..886519b2 100644
--- a/aarch64/PostpassSchedulingOracle.ml
+++ b/aarch64/PostpassSchedulingOracle.ml
@@ -203,6 +203,8 @@ let cvtx2w_real = Cvtx2w
 
 let is_XZR = function IREG0_XZR -> true | _ -> false
 
+let reg_of_pc = Reg Asm.PC
+
 let reg_of_dreg r = Reg (Asm.DR r)
 
 let reg_of_ireg r = Reg (Asm.DR (Asm.IR (Asm.RR1 r)))
@@ -348,7 +350,12 @@ let cvtuw2x_rec rd r1 =
   }
 
 let cvtx2w_rec rd =
-  { inst = cvtx2w_real; write_locs = []; read_locs = []; is_control = false }
+  {
+    inst = cvtx2w_real;
+    write_locs = [ rd ];
+    read_locs = [ rd ];
+    is_control = false;
+  }
 
 let get_testcond_rlocs c =
   match c with
@@ -401,14 +408,8 @@ let fnmul_rec fsz rd r1 r2 =
 let allocframe_rec sz linkofs =
   {
     inst = allocframe_real;
-    write_locs =
-      [
-        Mem;
-        regXSP;
-        reg_of_ireg Asm.X16;
-        reg_of_ireg Asm.X29;
-      ];
-    read_locs = [ regXSP ];
+    write_locs = [ Mem; regXSP; reg_of_ireg Asm.X16; reg_of_ireg Asm.X29 ];
+    read_locs = [ regXSP; Mem ];
     is_control = false;
   }
 
@@ -416,7 +417,7 @@ let freeframe_rec sz linkofs =
   {
     inst = freeframe_real;
     write_locs = [ Mem; regXSP; reg_of_ireg Asm.X16 ];
-    read_locs = [ Mem; regXSP ];
+    read_locs = [ regXSP; Mem ];
     is_control = false;
   }
 
@@ -455,8 +456,7 @@ let basic_rec i =
   | Ploadsymbol (rd, id) -> loadsymbol_rec (reg_of_ireg rd) id
   | Pcvtsw2x (rd, r1) -> cvtsw2x_rec (reg_of_ireg rd) (reg_of_ireg r1)
   | Pcvtuw2x (rd, r1) -> cvtuw2x_rec (reg_of_ireg rd) (reg_of_ireg r1)
-  (* XXX NYI in TargetPrinter? *)
-  | Pcvtx2w rd -> cvtx2w_rec rd
+  | Pcvtx2w rd -> cvtx2w_rec (reg_of_ireg rd)
 
 let builtin_rec ef args res =
   (* XXX verify this *)
@@ -470,74 +470,88 @@ let builtin_rec ef args res =
 let ctl_flow_rec i =
   match i with
   | Pb lbl ->
-      { inst = b_real; write_locs = []; read_locs = []; is_control = true }
+      {
+        inst = b_real;
+        write_locs = [ reg_of_pc ];
+        read_locs = [ reg_of_pc ];
+        is_control = true;
+      }
   | Pbc (c, lbl) ->
-      { inst = bc_real; write_locs = []; read_locs = []; is_control = true }
+      {
+        inst = bc_real;
+        write_locs = [ reg_of_pc ];
+        read_locs = [ reg_of_pc ];
+        is_control = true;
+      }
   | Pbl (id, sg) ->
       {
         inst = bl_real;
-        write_locs = [ reg_of_ireg Asm.X30 ];
-        read_locs = [];
+        write_locs = [ reg_of_ireg Asm.X30; reg_of_pc ];
+        read_locs = [ reg_of_pc ];
         is_control = true;
       }
       (* XXX not sure about X30 *)
   | Pbs (id, sg) ->
-      { inst = bs_real; write_locs = []; read_locs = []; is_control = true }
+      {
+        inst = bs_real;
+        write_locs = [ reg_of_pc ];
+        read_locs = [];
+        is_control = true;
+      }
   | Pblr (r, sg) ->
       {
         inst = blr_real;
-        write_locs = [ reg_of_ireg Asm.X30 ];
+        write_locs = [ reg_of_ireg Asm.X30; reg_of_pc ];
         read_locs = [ reg_of_ireg r ];
         is_control = true;
       }
-      (* XXX not sure about X30 *)
   | Pbr (r, sg) ->
       {
         inst = br_real;
-        write_locs = [];
+        write_locs = [ reg_of_pc ];
         read_locs = [ reg_of_ireg r ];
         is_control = true;
       }
   | Pret r ->
       {
         inst = ret_real;
-        write_locs = [];
+        write_locs = [ reg_of_pc ];
         read_locs = [ reg_of_ireg r ];
         is_control = true;
       }
   | Pcbnz (sz, r, lbl) ->
       {
         inst = cbnz_real;
-        write_locs = [];
-        read_locs = [ reg_of_ireg r ];
+        write_locs = [ reg_of_pc ];
+        read_locs = [ reg_of_ireg r; reg_of_pc ];
         is_control = true;
       }
   | Pcbz (sz, r, lbl) ->
       {
         inst = cbz_real;
-        write_locs = [];
-        read_locs = [ reg_of_ireg r ];
+        write_locs = [ reg_of_pc ];
+        read_locs = [ reg_of_ireg r; reg_of_pc ];
         is_control = true;
       }
   | Ptbnz (sz, r, n, lbl) ->
       {
         inst = tbnz_real;
-        write_locs = [];
-        read_locs = [ reg_of_ireg r ];
+        write_locs = [ reg_of_pc ];
+        read_locs = [ reg_of_ireg r; reg_of_pc ];
         is_control = true;
       }
   | Ptbz (sz, r, n, lbl) ->
       {
         inst = tbz_real;
-        write_locs = [];
-        read_locs = [ reg_of_ireg r ];
+        write_locs = [ reg_of_pc ];
+        read_locs = [ reg_of_ireg r; reg_of_pc ];
         is_control = true;
       }
   | Pbtbl (r1, tbl) ->
       {
         inst = btbl_real;
-        write_locs = [ reg_of_ireg Asm.X16; reg_of_ireg Asm.X17 ];
-        read_locs = [ reg_of_ireg r1 ];
+        write_locs = [ reg_of_ireg Asm.X16; reg_of_ireg Asm.X17; reg_of_pc ];
+        read_locs = [ reg_of_ireg r1; reg_of_pc ];
         is_control = true;
       }