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authorDavid Monniaux <david.monniaux@univ-grenoble-alpes.fr>2020-01-14 23:37:20 +0100
committerDavid Monniaux <david.monniaux@univ-grenoble-alpes.fr>2020-01-14 23:37:20 +0100
commit9475c5637c5d650f43955abe8f995797893affe1 (patch)
treea2993fa705e3d069ce280958df5e10f6f52d15fa /arm/Asmgen.v
parentb92d5a32c314eee0c68a70c33f1847545aabeb19 (diff)
downloadcompcert-kvx-9475c5637c5d650f43955abe8f995797893affe1.tar.gz
compcert-kvx-9475c5637c5d650f43955abe8f995797893affe1.zip
ARM generation of 2-instruction signed division by 2 (as opposed to 3-instruction)
Diffstat (limited to 'arm/Asmgen.v')
-rw-r--r--arm/Asmgen.v3
1 files changed, 3 insertions, 0 deletions
diff --git a/arm/Asmgen.v b/arm/Asmgen.v
index 1a1e7f2f..0ec0a4d0 100644
--- a/arm/Asmgen.v
+++ b/arm/Asmgen.v
@@ -481,6 +481,9 @@ Definition transl_op
do r <- ireg_of res; do r1 <- ireg_of a1;
if Int.eq n Int.zero then
OK (Pmov r (SOreg r1) :: k)
+ else if Int.eq n Int.one then
+ OK (Padd IR14 r1 (SOlsr r1 (Int.repr 31)) ::
+ Pmov r (SOasr IR14 n) :: k)
else
OK (Pmov IR14 (SOasr r1 (Int.repr 31)) ::
Padd IR14 r1 (SOlsr IR14 (Int.sub Int.iwordsize n)) ::