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author | Xavier Leroy <xavier.leroy@inria.fr> | 2017-04-28 15:56:59 +0200 |
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committer | Xavier Leroy <xavier.leroy@inria.fr> | 2017-04-28 16:05:51 +0200 |
commit | f642817f0dc761e51c3bd362f75b0068a8d4b0c8 (patch) | |
tree | b5830bb772611d2271c4b7d26f162d5c200dd788 /backend/SelectDiv.vp | |
parent | 2fbdb0c45f0913b9fd8e95606c525fc5bfb3bc6d (diff) | |
download | compcert-kvx-f642817f0dc761e51c3bd362f75b0068a8d4b0c8.tar.gz compcert-kvx-f642817f0dc761e51c3bd362f75b0068a8d4b0c8.zip |
RISC-V port and assorted changes
This commits adds code generation for the RISC-V architecture, both in 32- and 64-bit modes.
The generated code was lightly tested using the simulator and cross-binutils from https://riscv.org/software-tools/
This port required the following additional changes:
- Integers: More properties about shrx
- SelectOp: now provides smart constructors for mulhs and mulhu
- SelectDiv, 32-bit integer division and modulus: implement constant propagation, use the new smart constructors mulhs and mulhu.
- Runtime library: if no asm implementation is provided, run the reference C implementation through CompCert. Since CompCert rejects the definitions of names of special functions such as __i64_shl, the reference implementation now uses "i64_" names, e.g. "i64_shl", and a renaming "i64_ -> __i64_" is performed over the generated assembly file, before assembling and building the runtime library.
- test/: add SIMU make variable to run tests through a simulator
- test/regression/alignas.c: make sure _Alignas and _Alignof are not #define'd by C headers
commit da14495c01cf4f66a928c2feff5c53f09bde837f
Author: Xavier Leroy <xavier.leroy@inria.fr>
Date: Thu Apr 13 17:36:10 2017 +0200
RISC-V port, continued
Now working on Asmgen.
commit 36f36eb3a5abfbb8805960443d087b6a83e86005
Author: Xavier Leroy <xavier.leroy@inria.fr>
Date: Wed Apr 12 17:26:39 2017 +0200
RISC-V port, first steps
This port is based on Prashanth Mundkur's experimental RV32 port and brings it up to date with CompCert, and adds 64-bit support (RV64). Work in progress.
Diffstat (limited to 'backend/SelectDiv.vp')
-rw-r--r-- | backend/SelectDiv.vp | 58 |
1 files changed, 40 insertions, 18 deletions
diff --git a/backend/SelectDiv.vp b/backend/SelectDiv.vp index dc85fb25..96b07e28 100644 --- a/backend/SelectDiv.vp +++ b/backend/SelectDiv.vp @@ -19,6 +19,12 @@ Require Import Op CminorSel SelectOp SplitLong SelectLong. Local Open Scope cminorsel_scope. +Definition is_intconst (e: expr) : option int := + match e with + | Eop (Ointconst n) _ => Some n + | _ => None + end. + (** We try to turn divisions by a constant into a multiplication by a pseudo-inverse of the divisor. The approach is described in - Torbjörn Granlund, Peter L. Montgomery: "Division by Invariant @@ -101,7 +107,7 @@ Definition divlu_mul_params (d: Z) : option (Z * Z) := end. Definition divu_mul (p: Z) (m: Z) := - shruimm (Eop Omulhu (Eletvar O ::: Eop (Ointconst (Int.repr m)) Enil ::: Enil)) + shruimm (mulhu (Eletvar O) (Eop (Ointconst (Int.repr m)) Enil)) (Int.repr p). Definition divuimm (e1: expr) (n2: int) := @@ -117,10 +123,14 @@ Definition divuimm (e1: expr) (n2: int) := end end. -Nondetfunction divu (e1: expr) (e2: expr) := - match e2 with - | Eop (Ointconst n2) Enil => divuimm e1 n2 - | _ => divu_base e1 e2 +Definition divu (e1: expr) (e2: expr) := + match is_intconst e2, is_intconst e1 with + | Some n2, Some n1 => + if Int.eq n2 Int.zero + then divu_base e1 e2 + else Eop (Ointconst (Int.divu n1 n2)) Enil + | Some n2, _ => divuimm e1 n2 + | _, _ => divu_base e1 e2 end. Definition mod_from_div (equo: expr) (n: int) := @@ -139,15 +149,19 @@ Definition moduimm (e1: expr) (n2: int) := end end. -Nondetfunction modu (e1: expr) (e2: expr) := - match e2 with - | Eop (Ointconst n2) Enil => moduimm e1 n2 - | _ => modu_base e1 e2 +Definition modu (e1: expr) (e2: expr) := + match is_intconst e2, is_intconst e1 with + | Some n2, Some n1 => + if Int.eq n2 Int.zero + then modu_base e1 e2 + else Eop (Ointconst (Int.modu n1 n2)) Enil + | Some n2, _ => moduimm e1 n2 + | _, _ => modu_base e1 e2 end. Definition divs_mul (p: Z) (m: Z) := let e2 := - Eop Omulhs (Eletvar O ::: Eop (Ointconst (Int.repr m)) Enil ::: Enil) in + mulhs (Eletvar O) (Eop (Ointconst (Int.repr m)) Enil) in let e3 := if zlt m Int.half_modulus then e2 else add e2 (Eletvar O) in add (shrimm e3 (Int.repr p)) @@ -169,10 +183,14 @@ Definition divsimm (e1: expr) (n2: int) := end end. -Nondetfunction divs (e1: expr) (e2: expr) := - match e2 with - | Eop (Ointconst n2) Enil => divsimm e1 n2 - | _ => divs_base e1 e2 +Definition divs (e1: expr) (e2: expr) := + match is_intconst e2, is_intconst e1 with + | Some n2, Some n1 => + if Int.eq n2 Int.zero + then divs_base e1 e2 + else Eop (Ointconst (Int.divs n1 n2)) Enil + | Some n2, _ => divsimm e1 n2 + | _, _ => divs_base e1 e2 end. Definition modsimm (e1: expr) (n2: int) := @@ -191,10 +209,14 @@ Definition modsimm (e1: expr) (n2: int) := end end. -Nondetfunction mods (e1: expr) (e2: expr) := - match e2 with - | Eop (Ointconst n2) Enil => modsimm e1 n2 - | _ => mods_base e1 e2 +Definition mods (e1: expr) (e2: expr) := + match is_intconst e2, is_intconst e1 with + | Some n2, Some n1 => + if Int.eq n2 Int.zero + then mods_base e1 e2 + else Eop (Ointconst (Int.mods n1 n2)) Enil + | Some n2, _ => modsimm e1 n2 + | _, _ => mods_base e1 e2 end. (** 64-bit integer divisions *) |