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authorCyril SIX <cyril.six@kalray.eu>2021-06-18 18:35:50 +0200
committerCyril SIX <cyril.six@kalray.eu>2021-06-18 18:35:50 +0200
commit5798f56b8a8630e43dbed84a824811a5626a1503 (patch)
treebee034c6b707a83a4e3e969650c2e2fc6ccb6358 /kvx/Asmvliw.v
parent04b2489d7c2a9b0d203b3d431517367a07bd6b30 (diff)
downloadcompcert-kvx-5798f56b8a8630e43dbed84a824811a5626a1503.tar.gz
compcert-kvx-5798f56b8a8630e43dbed84a824811a5626a1503.zip
Replacing default notrap load value by Vundef everywherecsix-PhD
Diffstat (limited to 'kvx/Asmvliw.v')
-rw-r--r--kvx/Asmvliw.v11
1 files changed, 5 insertions, 6 deletions
diff --git a/kvx/Asmvliw.v b/kvx/Asmvliw.v
index 304e45a8..45b230e6 100644
--- a/kvx/Asmvliw.v
+++ b/kvx/Asmvliw.v
@@ -313,7 +313,6 @@ Inductive cf_instruction : Type :=
.
(** *** Loads *)
-Definition concrete_default_notrap_load_value (chunk : memory_chunk) := Vundef.
(* What follows was the original spec, but is subtly incorrect.
Our definition of the assembly-level memory model is already an abstraction of the real world.
@@ -1174,16 +1173,16 @@ Definition eval_offset (ofs: offset) : res ptrofs := OK ofs.
(** *** load/store instructions *)
-Definition parexec_incorrect_load trap chunk d rsw mw :=
+Definition parexec_incorrect_load trap d rsw mw :=
match trap with
| TRAP => Stuck
- | NOTRAP => Next (rsw#d <- (concrete_default_notrap_load_value chunk)) mw
+ | NOTRAP => Next (rsw#d <- Vundef) mw
end.
Definition parexec_load_offset (trap: trapping_mode) (chunk: memory_chunk) (rsr rsw: regset) (mr mw: mem) (d a: ireg) (ofs: offset) :=
match (eval_offset ofs) with
| OK ptr => match Mem.loadv chunk mr (Val.offset_ptr (rsr a) ptr) with
- | None => parexec_incorrect_load trap chunk d rsw mw
+ | None => parexec_incorrect_load trap d rsw mw
| Some v => Next (rsw#d <- v) mw
end
| _ => Stuck
@@ -1230,13 +1229,13 @@ Definition parexec_load_o_offset (rsr rsw: regset) (mr mw: mem) (d : gpreg_o) (a
Definition parexec_load_reg (trap: trapping_mode) (chunk: memory_chunk) (rsr rsw: regset) (mr mw: mem) (d a ro: ireg) :=
match Mem.loadv chunk mr (Val.addl (rsr a) (rsr ro)) with
- | None => parexec_incorrect_load trap chunk d rsw mw
+ | None => parexec_incorrect_load trap d rsw mw
| Some v => Next (rsw#d <- v) mw
end.
Definition parexec_load_regxs (trap: trapping_mode) (chunk: memory_chunk) (rsr rsw: regset) (mr mw: mem) (d a ro: ireg) :=
match Mem.loadv chunk mr (Val.addl (rsr a) (Val.shll (rsr ro) (scale_of_chunk chunk))) with
- | None => parexec_incorrect_load trap chunk d rsw mw
+ | None => parexec_incorrect_load trap d rsw mw
| Some v => Next (rsw#d <- v) mw
end.