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authornicolas.nardino <nicolas.nardino@ens-lyon.fr>2021-06-22 15:58:10 +0200
committernicolas.nardino <nicolas.nardino@ens-lyon.fr>2021-06-22 15:58:10 +0200
commitc5e8595480604c78260017cc771b0e4195fdd182 (patch)
treee7a05088dd8ad7003367be4c832bf5967ab92523 /kvx/Asmvliw.v
parent10cbe4b28ef6dc5d02c9a5d4d369484e4943a18d (diff)
parentcf2aa686bcf9a823562fe977df6dd778d5467985 (diff)
downloadcompcert-kvx-c5e8595480604c78260017cc771b0e4195fdd182.tar.gz
compcert-kvx-c5e8595480604c78260017cc771b0e4195fdd182.zip
Merge branch 'kvx-sched-w-reg-press' of gricad-gitlab.univ-grenoble-alpes.fr:sixcy/CompCert into kvx-sched-w-reg-press
Diffstat (limited to 'kvx/Asmvliw.v')
-rw-r--r--kvx/Asmvliw.v9
1 files changed, 7 insertions, 2 deletions
diff --git a/kvx/Asmvliw.v b/kvx/Asmvliw.v
index aa2e0885..304e45a8 100644
--- a/kvx/Asmvliw.v
+++ b/kvx/Asmvliw.v
@@ -313,7 +313,12 @@ Inductive cf_instruction : Type :=
.
(** *** Loads *)
-Definition concrete_default_notrap_load_value (chunk : memory_chunk) :=
+Definition concrete_default_notrap_load_value (chunk : memory_chunk) := Vundef.
+
+(* What follows was the original spec, but is subtly incorrect.
+ Our definition of the assembly-level memory model is already an abstraction of the real world.
+ In particular, we consider that a load is incorrect when it points outside of CompCert's visible memory, whereas this memory could be correct at the assembly level.
+ This means that CompCert would believe an incorrect load would yield 0 whereas it would yield another value.
match chunk with
| Mint8signed | Mint8unsigned | Mint16signed | Mint16unsigned
| Mint32 => Vint Int.zero
@@ -321,7 +326,7 @@ Definition concrete_default_notrap_load_value (chunk : memory_chunk) :=
| Many32 | Many64 => Vundef
| Mfloat32 => Vsingle Float32.zero
| Mfloat64 => Vfloat Float.zero
- end.
+ end. *)
Inductive load_name : Type :=
| Plb (**r load byte *)