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author | David Monniaux <David.Monniaux@univ-grenoble-alpes.fr> | 2022-02-14 15:48:43 +0100 |
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committer | David Monniaux <David.Monniaux@univ-grenoble-alpes.fr> | 2022-02-14 15:48:43 +0100 |
commit | f6686d81092ccaaf3a22b4e34aecc7c5895b08ba (patch) | |
tree | 9d61868c2ad5e0ed20329512d9508280da1e4c70 /kvx/PostpassSchedulingOracle.ml | |
parent | b7aea86a0c6ace274e585fddfd0d88d13528cc90 (diff) | |
download | compcert-kvx-f6686d81092ccaaf3a22b4e34aecc7c5895b08ba.tar.gz compcert-kvx-f6686d81092ccaaf3a22b4e34aecc7c5895b08ba.zip |
begin adding abdw abdd
Diffstat (limited to 'kvx/PostpassSchedulingOracle.ml')
-rw-r--r-- | kvx/PostpassSchedulingOracle.ml | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/kvx/PostpassSchedulingOracle.ml b/kvx/PostpassSchedulingOracle.ml index 47849dd5..3eb0b95f 100644 --- a/kvx/PostpassSchedulingOracle.ml +++ b/kvx/PostpassSchedulingOracle.ml @@ -34,6 +34,7 @@ type real_instruction = | Addw | Andw | Compw | Mulw | Orw | Sbfw | Sbfxw | Sraw | Srlw | Sllw | Srsw | Rorw | Xorw | Addd | Andd | Compd | Muld | Ord | Sbfd | Sbfxd | Srad | Srld | Slld | Srsd | Xord | Nandw | Norw | Nxorw | Nandd | Nord | Nxord | Andnw | Ornw | Andnd | Ornd + | Abdw | Abdd | Maddw | Maddd | Msbfw | Msbfd | Cmoved | Make | Nop | Extfz | Extfs | Insf | Addxw | Addxd @@ -143,6 +144,8 @@ let arith_rrr_real = function | Pfminw -> Fminw | Pfmaxd -> Fmaxd | Pfmaxw -> Fmaxw + | Pabdw -> Abdw + | Pabdl -> Abdd let arith_rri32_real = function | Pcompiw it -> Compw @@ -168,6 +171,7 @@ let arith_rri32_real = function | Psrlil -> Srld | Psrail -> Srad | Psrxil -> Srsd + | Pabdiw -> Abdw let arith_rri64_real = function | Pcompil it -> Compd @@ -184,6 +188,7 @@ let arith_rri64_real = function | Pnxoril -> Nxord | Pandnil -> Andnd | Pornil -> Ornd + | Pabdil -> Abdd let arith_arr_real = function @@ -603,11 +608,11 @@ let rec_to_usage r = (match encoding with None | Some U6 | Some S10 -> alu_lite | Some U27L5 | Some U27L10 -> alu_lite_x | Some E27U27L10 -> alu_lite_y) - | Addxw -> + | Addxw | Abdw -> (match encoding with None | Some U6 | Some S10 -> alu_lite | Some U27L5 | Some U27L10 -> alu_lite_x | _ -> raise InvalidEncoding) - | Addxd -> + | Addxd | Abdd -> (match encoding with None | Some U6 | Some S10 -> alu_lite | Some U27L5 | Some U27L10 -> alu_lite_x | Some E27U27L10 -> alu_lite_y) @@ -681,6 +686,7 @@ let real_inst_to_latency = function | Addd | Andd | Compd | Ord | Sbfd | Sbfxd | Srad | Srsd | Srld | Slld | Xord | Make | Extfs | Extfz | Insf | Fcompw | Fcompd | Cmoved | Addxw | Addxd | Fmind | Fmaxd | Fminw | Fmaxw + | Abdw | Abdd -> 1 | Floatwz | Floatuwz | Fixeduw | Fixedw | Floatdz | Floatudz | Fixedd | Fixedud -> 4 | Mulw | Muld | Maddw | Maddd | Msbfw | Msbfd -> 2 (* FIXME - WORST CASE. If it's S10 then it's only 1 *) |