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authorCyril SIX <cyril.six@univ-grenoble-alpes.fr>2019-04-25 18:33:21 +0200
committerCyril SIX <cyril.six@univ-grenoble-alpes.fr>2019-04-25 18:33:21 +0200
commitbb7f6223911e354720709d623c5d9510319fb8b3 (patch)
treed6e02863c343b67fcce45fd6093faf0e2d3c9b67 /mppa_k1c/InstructionScheduler.mli
parent6d1223d053f1ff10792d5ed5d00d3830ff61e9d7 (diff)
downloadcompcert-kvx-bb7f6223911e354720709d623c5d9510319fb8b3.tar.gz
compcert-kvx-bb7f6223911e354720709d623c5d9510319fb8b3.zip
[BUGGED] First attempt at a dumb scheduler ("accumulates" instructions)
Diffstat (limited to 'mppa_k1c/InstructionScheduler.mli')
-rw-r--r--mppa_k1c/InstructionScheduler.mli3
1 files changed, 3 insertions, 0 deletions
diff --git a/mppa_k1c/InstructionScheduler.mli b/mppa_k1c/InstructionScheduler.mli
index 629664f9..701ccb25 100644
--- a/mppa_k1c/InstructionScheduler.mli
+++ b/mppa_k1c/InstructionScheduler.mli
@@ -62,6 +62,9 @@ Once a clock tick is full go to the next.
@return [Some solution] when a solution is found, [None] if not. *)
val list_scheduler : problem -> solution option
+(** Schedule the problem using the order of instructions without any reordering *)
+val dumb_scheduler : problem -> solution option
+
(** Schedule a problem using a scheduler applied in the opposite direction, e.g. for list scheduling from the end instead of the start. BUGGY *)
val schedule_reversed : scheduler -> problem -> int array option