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authorCyril SIX <cyril.six@kalray.eu>2019-05-03 10:43:53 +0200
committerCyril SIX <cyril.six@kalray.eu>2019-05-03 10:43:53 +0200
commitfb77ce264f957a1ee3f87e537b55afbb10785ecf (patch)
treee65797eee4cac155a9c87b2ca0ed35b2bb848bdf /mppa_k1c/InstructionScheduler.mli
parent6783207fa4282f53af1da8bf09e4819716acde64 (diff)
downloadcompcert-kvx-fb77ce264f957a1ee3f87e537b55afbb10785ecf.tar.gz
compcert-kvx-fb77ce264f957a1ee3f87e537b55afbb10785ecf.zip
Renaming "dumb" scheduling into "greedy"
Diffstat (limited to 'mppa_k1c/InstructionScheduler.mli')
-rw-r--r--mppa_k1c/InstructionScheduler.mli2
1 files changed, 1 insertions, 1 deletions
diff --git a/mppa_k1c/InstructionScheduler.mli b/mppa_k1c/InstructionScheduler.mli
index 701ccb25..f91c2d06 100644
--- a/mppa_k1c/InstructionScheduler.mli
+++ b/mppa_k1c/InstructionScheduler.mli
@@ -63,7 +63,7 @@ Once a clock tick is full go to the next.
val list_scheduler : problem -> solution option
(** Schedule the problem using the order of instructions without any reordering *)
-val dumb_scheduler : problem -> solution option
+val greedy_scheduler : problem -> solution option
(** Schedule a problem using a scheduler applied in the opposite direction, e.g. for list scheduling from the end instead of the start. BUGGY *)
val schedule_reversed : scheduler -> problem -> int array option