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| author | David Monniaux <david.monniaux@univ-grenoble-alpes.fr> | 2019-02-13 15:18:23 +0100 |
|---|---|---|
| committer | David Monniaux <david.monniaux@univ-grenoble-alpes.fr> | 2019-02-13 15:18:23 +0100 |
| commit | 6597c681b6e5273a8b6ad4644186abfe7082942d (patch) | |
| tree | 264e264336d726926361321c1ab95083c57e57b5 /mppa_k1c/PostpassSchedulingOracle.ml | |
| parent | 2f33dd16ce2f1ac423076b217c71f105ac5e66c8 (diff) | |
| parent | 706937c529543fed0c522fe28c1f32ec08ddea09 (diff) | |
| download | compcert-kvx-6597c681b6e5273a8b6ad4644186abfe7082942d.tar.gz compcert-kvx-6597c681b6e5273a8b6ad4644186abfe7082942d.zip | |
Merge branch 'mppa_postpass' of gricad-gitlab.univ-grenoble-alpes.fr:sixcy/CompCert into mppa_postpass
Diffstat (limited to 'mppa_k1c/PostpassSchedulingOracle.ml')
| -rw-r--r-- | mppa_k1c/PostpassSchedulingOracle.ml | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/mppa_k1c/PostpassSchedulingOracle.ml b/mppa_k1c/PostpassSchedulingOracle.ml index fa11a298..9126d230 100644 --- a/mppa_k1c/PostpassSchedulingOracle.ml +++ b/mppa_k1c/PostpassSchedulingOracle.ml @@ -34,6 +34,10 @@ let arith_rr_str = function | Pfnegd -> "Pfnegd" | Psxwd -> "Psxwd" | Pzxwd -> "Pzxwd" + | Pfloatwrnsz -> "Pfloatwrnsz" + | Pfloatdrnsz -> "Pfloatdrnsz" + | Pfixedwrzz -> "Pfixedwrzz" + | Pfixeddrzz -> "Pfixeddrzz" let arith_rrr_str = function | Pcompw it -> "Pcompw" @@ -81,6 +85,10 @@ let arith_ri32_str = "Pmake" let arith_ri64_str = "Pmakel" +let arith_rf32_str = "Pmakefs" + +let arith_rf64_str = "Pmakef" + let store_str = function | Psb -> "Psb" | Psh -> "Psh" @@ -127,6 +135,10 @@ let arith_rec i = | PArithRRR (i, rd, rs1, rs2) -> arith_rrr_rec i (IR rd) (IR rs1) (IR rs2) | PArithRI32 (rd, imm32) -> { inst = arith_ri32_str; write_locs = [Reg (IR rd)]; read_locs = []; imm = (Some (I32 imm32)) ; is_control = false} | PArithRI64 (rd, imm64) -> { inst = arith_ri64_str; write_locs = [Reg (IR rd)]; read_locs = []; imm = (Some (I64 imm64)) ; is_control = false} + | PArithRF32 (rd, f) -> { inst = arith_rf32_str; write_locs = [Reg (IR rd)]; read_locs = []; + imm = (Some (I32 (Floats.Float32.to_bits f))); is_control = false} + | PArithRF64 (rd, f) -> { inst = arith_rf64_str; write_locs = [Reg (IR rd)]; read_locs = []; + imm = (Some (I64 (Floats.Float.to_bits f))); is_control = false} | PArithRR (i, rd, rs) -> arith_rr_rec i (IR rd) (IR rs) | PArithR (i, rd) -> arith_r_rec i (IR rd) @@ -335,7 +347,7 @@ type real_instruction = (* BCU *) | Icall | Call | Cb | Igoto | Goto | Ret | Get | Set (* FPU *) - | Fnegd + | Fnegd | Floatwz | Floatdz | Fixedwz | Fixeddz let ab_inst_to_real = function | "Paddw" | "Paddiw" | "Pcvtl2w" -> Addw @@ -358,10 +370,14 @@ let ab_inst_to_real = function | "Pslll" | "Psllil" -> Slld | "Pxorw" | "Pxoriw" -> Xorw | "Pxorl" | "Pxoril" -> Xord - | "Pmake" | "Pmakel" | "Ploadsymbol" -> Make + | "Pmake" | "Pmakel" | "Pmakefs" | "Pmakef" | "Ploadsymbol" -> Make | "Pnop" | "Pcvtw2l" -> Nop | "Psxwd" -> Sxwd | "Pzxwd" -> Zxwd + | "Pfloatwrnsz" -> Floatwz + | "Pfloatdrnsz" -> Floatdz + | "Pfixedwrzz" -> Fixedwz + | "Pfixeddrzz" -> Fixeddz | "Plb" -> Lbs | "Plbu" -> Lbz @@ -423,6 +439,7 @@ let rec_to_usage r = | Nop -> alu_nop | Sraw | Srlw | Sllw | Srad | Srld | Slld -> (match encoding with None | Some U6 -> alu_tiny | _ -> raise InvalidEncoding) | Sxwd | Zxwd -> (match encoding with None -> alu_lite | _ -> raise InvalidEncoding) + | Fixedwz | Floatwz | Fixeddz | Floatdz -> mau | Lbs | Lbz | Lhs | Lhz | Lws | Ld -> (match encoding with None | Some U6 | Some S10 -> lsu_data | Some U27L5 | Some U27L10 -> lsu_data_x @@ -441,6 +458,7 @@ let real_inst_to_latency = function | Addd | Andd | Compd | Ord | Sbfd | Srad | Srld | Slld | Xord | Make | Sxwd | Zxwd -> 1 + | Floatwz | Fixedwz | Floatdz | Fixeddz -> 4 | Mulw | Muld -> 2 (* FIXME - WORST CASE. If it's S10 then it's only 1 *) | Lbs | Lbz | Lhs | Lhz | Lws | Ld | Sb | Sh | Sw | Sd |