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| author | Cyril SIX <cyril.six@kalray.eu> | 2018-04-17 17:03:52 +0200 |
|---|---|---|
| committer | Cyril SIX <cyril.six@kalray.eu> | 2018-04-17 17:03:52 +0200 |
| commit | b63085295d8495ff640f5eaff8b8ad52fc5c43d1 (patch) | |
| tree | fb854f158307f9a5185e92959e63df470566d538 /mppa_k1c/TargetPrinter.ml | |
| parent | b17acc2e5f9c31a93164897c64c698fe8e490765 (diff) | |
| download | compcert-kvx-b63085295d8495ff640f5eaff8b8ad52fc5c43d1.tar.gz compcert-kvx-b63085295d8495ff640f5eaff8b8ad52fc5c43d1.zip | |
MPPA - More shifts
Diffstat (limited to 'mppa_k1c/TargetPrinter.ml')
| -rw-r--r-- | mppa_k1c/TargetPrinter.ml | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/mppa_k1c/TargetPrinter.ml b/mppa_k1c/TargetPrinter.ml index 0f242eda..977d3019 100644 --- a/mppa_k1c/TargetPrinter.ml +++ b/mppa_k1c/TargetPrinter.ml @@ -223,12 +223,20 @@ module Target : TARGET = fprintf oc " srld %a = %a, %a\n;;\n" ireg rd ireg rs coqint64 imm | Psrll (rd, rs1, rs2) -> fprintf oc " srld %a = %a, %a\n;;\n" ireg rd ireg rs1 ireg rs2 + | Psrlw (rd, rs1, rs2) -> + fprintf oc " srlw %a = %a, %a\n;;\n" ireg rd ireg rs1 ireg rs2 + | Pslliw (rd, rs, imm) -> + fprintf oc " sllw %a = %a, %a\n;;\n" ireg rd ireg rs coqint64 imm + | Psllw (rd, rs1, rs2) -> + fprintf oc " sllw %a = %a, %a\n;;\n" ireg rd ireg rs1 ireg rs2 | Psllil (rd, rs, imm) -> fprintf oc " slld %a = %a, %a\n;;\n" ireg rd ireg rs coqint64 imm | Pslll (rd, rs1, rs2) -> fprintf oc " slld %a = %a, %a\n;;\n" ireg rd ireg rs1 ireg rs2 | Psraw (rd, rs1, rs2) -> fprintf oc " sraw %a = %a, %a\n;;\n" ireg rd ireg rs1 ireg rs2 + | Psraiw (rd, rs1, imm) -> + fprintf oc " sraw %a = %a, %a\n;;\n" ireg rd ireg rs1 coqint64 imm | Psral (rd, rs1, rs2) -> fprintf oc " srad %a = %a, %a\n;;\n" ireg rd ireg rs1 ireg rs2 | Psrail (rd, rs1, imm) -> |