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| author | David Monniaux <david.monniaux@univ-grenoble-alpes.fr> | 2021-02-02 18:25:47 +0100 |
|---|---|---|
| committer | David Monniaux <david.monniaux@univ-grenoble-alpes.fr> | 2021-02-02 18:25:47 +0100 |
| commit | 90493ef36faa2925dbb107a994a57f010424fcbd (patch) | |
| tree | 776a00f2b792d084975474c3a6e785c1a9e4121a /riscV | |
| parent | afe54de36234834449e72d9dc891a90291aadcb1 (diff) | |
| download | compcert-kvx-90493ef36faa2925dbb107a994a57f010424fcbd.tar.gz compcert-kvx-90493ef36faa2925dbb107a994a57f010424fcbd.zip | |
fix code generation for select(b, r, r)
Diffstat (limited to 'riscV')
| -rw-r--r-- | riscV/Asmexpand.ml | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/riscV/Asmexpand.ml b/riscV/Asmexpand.ml index 14407bba..c5cd6817 100644 --- a/riscV/Asmexpand.ml +++ b/riscV/Asmexpand.ml @@ -591,8 +591,13 @@ let expand_instruction instr = else if ireg0_eq rt rf then begin - if not (ireg0_eq (X rd) rt) then - emit (Paddil(rd, rt, Int64.zero)) + if ireg0_eq (X rd) rt then + begin + end + else + begin + emit (Paddl(rd, X0, rt)) + end end else if (ireg0_eq (X rd) rt) then |