diff options
| author | nicolas.nardino <nicolas.nardino@ens-lyon.fr> | 2021-06-15 14:44:56 +0200 |
|---|---|---|
| committer | nicolas.nardino <nicolas.nardino@ens-lyon.fr> | 2021-06-15 14:44:56 +0200 |
| commit | 87c82b6fcf2bf825a8c60fc6a95498aac9f826d4 (patch) | |
| tree | 162a8642b85de5005ef7d63e50a789e73f6d6673 /scheduling/InstructionScheduler.ml | |
| parent | 19464b3992eadf7670acc7231896103ab54885e5 (diff) | |
| download | compcert-kvx-87c82b6fcf2bf825a8c60fc6a95498aac9f826d4.tar.gz compcert-kvx-87c82b6fcf2bf825a8c60fc6a95498aac9f826d4.zip | |
kinda fixed
Spills are definitely reduced, but lots of arbitrary in there:
See previous commit: need to determine what to do if pressure is too
high but no schedulable instruction can reduce it. For now, advance
time for at most 5 cycles, if still no suitable instruction, go back
to CSP
Diffstat (limited to 'scheduling/InstructionScheduler.ml')
| -rw-r--r-- | scheduling/InstructionScheduler.ml | 62 |
1 files changed, 40 insertions, 22 deletions
diff --git a/scheduling/InstructionScheduler.ml b/scheduling/InstructionScheduler.ml index 19bfaeb0..72222022 100644 --- a/scheduling/InstructionScheduler.ml +++ b/scheduling/InstructionScheduler.ml @@ -478,6 +478,9 @@ let reg_pres_scheduler (problem : problem) : solution option = ready.(!current_time) <- InstrSet.empty)); incr current_time in + + (* ALL MENTIONS TO cnt ARE PLACEHOLDERS *) + let cnt = ref 0 in let attempt_scheduling ready usages = let result = ref (-1) in @@ -488,8 +491,11 @@ let reg_pres_scheduler (problem : problem) : solution option = print_string " "; print_int avlregs; print_newline (); + print_string "live regs: "; + print_int (Hashtbl.length live_regs); + print_newline (); flush stdout; - if avlregs <= regs_thresholds.(i) + if !cnt < 5 && avlregs <= regs_thresholds.(i) then ( let maybe = InstrSet.sched_CSR i ready usages in print_string "maybe\n"; @@ -506,8 +512,9 @@ let reg_pres_scheduler (problem : problem) : solution option = delta >= 0 then (vector_subtract usages.(maybe) current_resources; - result := maybe; - raise Exit))) available_regs; + result := maybe) + else incr cnt; + raise Exit)) available_regs; InstrSet.iter (fun i -> if vector_less_equal usages.(i) current_resources then ( @@ -516,25 +523,7 @@ let reg_pres_scheduler (problem : problem) : solution option = raise Exit)) ready; -1 with Exit -> - if !result <> -1 then - (List.iter (fun (r,b) -> - if b then - match Hashtbl.find_opt counts r with - | None -> assert false - | Some (t, n) -> - Hashtbl.remove counts r; - (if n = 1 then - available_regs.(t) - <- available_regs.(t) + 1) - else - let t = class_r r in - match Hashtbl.find_opt live_regs r with - | None -> (Hashtbl.add live_regs r t; - available_regs.(t) - <- available_regs.(t) - 1) - | Some i -> () - ) mentions.(!result)); - !result in + !result in while !current_time < max_time do @@ -545,6 +534,35 @@ let reg_pres_scheduler (problem : problem) : solution option = problem.instruction_usages with | -1 -> advance_time() | i -> (assert(times.(i) < 0); + (print_string "INSTR ISSUED: "; + print_int i; + print_newline (); + flush stdout; + cnt := 0; + List.iter (fun (r,b) -> + if b then + (match Hashtbl.find_opt counts r with + | None -> assert false + | Some (t, n) -> + Hashtbl.remove counts r; + if n = 1 then + (print_string "yaaaaaaaaaaaas "; + print_int (Camlcoq.P.to_int r); + print_newline (); + Hashtbl.remove live_regs r; + available_regs.(t) + <- available_regs.(t) + 1)) + else + let t = class_r r in + match Hashtbl.find_opt live_regs r with + | None -> (print_string "noooooooooo "; + print_int (Camlcoq.P.to_int r); + print_newline (); + Hashtbl.add live_regs r t; + available_regs.(t) + <- available_regs.(t) - 1) + | Some i -> () + ) mentions.(i)); times.(i) <- !current_time; ready.(!current_time) <- InstrSet.remove i (ready.(!current_time)); |