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| author | David Monniaux <david.monniaux@univ-grenoble-alpes.fr> | 2019-03-22 08:08:44 +0100 |
|---|---|---|
| committer | David Monniaux <david.monniaux@univ-grenoble-alpes.fr> | 2019-03-22 08:08:44 +0100 |
| commit | ba2b825a42807102a93cd6df1ce90b41d415569c (patch) | |
| tree | 524791f9b646591b6afb9d1edaef906e7d32875a /x86 | |
| parent | c4661a0181e6db3aa4a36939bdbea5948eadb6c9 (diff) | |
| parent | 49ea6f7d4b9e18f8aa740d068bb3fb9e49596e00 (diff) | |
| download | compcert-kvx-ba2b825a42807102a93cd6df1ce90b41d415569c.tar.gz compcert-kvx-ba2b825a42807102a93cd6df1ce90b41d415569c.zip | |
Merge branch 'mppa_postpass' into mppa-mul
Diffstat (limited to 'x86')
| -rw-r--r-- | x86/Conventions1.v | 3 | ||||
| -rw-r--r-- | x86/Machregsaux.ml | 9 | ||||
| -rw-r--r-- | x86/Machregsaux.mli | 2 |
3 files changed, 11 insertions, 3 deletions
diff --git a/x86/Conventions1.v b/x86/Conventions1.v index 646c4afb..35d555f9 100644 --- a/x86/Conventions1.v +++ b/x86/Conventions1.v @@ -15,6 +15,7 @@ Require Import Coqlib Decidableplus. Require Import AST Machregs Locations. +Require Import Errors. (** * Classification of machine registers *) @@ -26,7 +27,7 @@ Require Import AST Machregs Locations. We follow the x86-32 and x86-64 application binary interfaces (ABI) in our choice of callee- and caller-save registers. *) - + Definition is_callee_save (r: mreg) : bool := match r with | AX | CX | DX => false diff --git a/x86/Machregsaux.ml b/x86/Machregsaux.ml index 473e0602..80066b00 100644 --- a/x86/Machregsaux.ml +++ b/x86/Machregsaux.ml @@ -14,9 +14,9 @@ open Camlcoq open Machregs - + let register_names : (mreg, string) Hashtbl.t = Hashtbl.create 31 - + let _ = List.iter (fun (s, r) -> Hashtbl.add register_names r (camlstring_of_coqstring s)) @@ -31,3 +31,8 @@ let register_by_name s = Machregs.register_by_name (coqstring_uppercase_ascii_of_camlstring s) let can_reserve_register r = Conventions1.is_callee_save r + +let class_of_type = function + | AST.Tint | AST.Tlong -> 0 + | AST.Tfloat | AST.Tsingle -> 1 + | AST.Tany32 | AST.Tany64 -> assert false diff --git a/x86/Machregsaux.mli b/x86/Machregsaux.mli index 9404568d..d7117c21 100644 --- a/x86/Machregsaux.mli +++ b/x86/Machregsaux.mli @@ -16,3 +16,5 @@ val name_of_register: Machregs.mreg -> string option val register_by_name: string -> Machregs.mreg option val is_scratch_register: string -> bool val can_reserve_register: Machregs.mreg -> bool + +val class_of_type: AST.typ -> int |