diff options
| -rw-r--r-- | powerpc/Asm.v | 4 | ||||
| -rw-r--r-- | powerpc/AsmToJSON.ml | 2 | ||||
| -rw-r--r-- | powerpc/Asmexpand.ml | 11 | ||||
| -rw-r--r-- | powerpc/CBuiltins.ml | 2 | ||||
| -rw-r--r-- | powerpc/Machregs.v | 2 | ||||
| -rw-r--r-- | powerpc/TargetPrinter.ml | 4 |
6 files changed, 25 insertions, 0 deletions
diff --git a/powerpc/Asm.v b/powerpc/Asm.v index 589d66fe..dbb819d1 100644 --- a/powerpc/Asm.v +++ b/powerpc/Asm.v @@ -167,6 +167,8 @@ Inductive instruction : Type := | Pcrxor: crbit -> crbit -> crbit -> instruction (**r xor between condition bits *) | Pdcbf: ireg -> ireg -> instruction (**r data cache flush *) | Pdcbi: ireg -> ireg -> instruction (**r data cache invalidate *) + | Pdcbt: int -> ireg -> instruction (**r data cache block touch *) + | Pdcbtst: int -> ireg -> instruction (**r data cache block touch *) | Pdivw: ireg -> ireg -> ireg -> instruction (**r signed division *) | Pdivwu: ireg -> ireg -> ireg -> instruction (**r unsigned division *) | Peieio: instruction (**r EIEIO barrier *) @@ -870,6 +872,8 @@ Definition exec_instr (f: function) (i: instruction) (rs: regset) (m: mem) : out | Pcrxor _ _ _ | Pdcbf _ _ | Pdcbi _ _ + | Pdcbt _ _ + | Pdcbtst _ _ | Peieio | Pfctiw _ _ | Pfctiwz _ _ diff --git a/powerpc/AsmToJSON.ml b/powerpc/AsmToJSON.ml index 3440e16f..fb73aec5 100644 --- a/powerpc/AsmToJSON.ml +++ b/powerpc/AsmToJSON.ml @@ -177,6 +177,8 @@ let p_instruction oc ic = | Pcrxor (cr1,cr2,cr3) -> fprintf oc "{\"Instruction Name\":\"Pcrxor\",\"Args\":[%a,%a,%a]}" p_crbit cr1 p_crbit cr2 p_crbit cr3 | Pdcbf (ir1,ir2) -> fprintf oc "{\"Instruction Name\":\"Pdcbf\",\"Args\":[%a,%a]}" p_ireg ir1 p_ireg ir2 | Pdcbi (ir1,ir2) -> fprintf oc "{\"Instruction Name\":\"Pdcbi\",\"Args\":[%a,%a]}" p_ireg ir1 p_ireg ir2 + | Pdcbt (n,ir1) -> fprintf oc "{\"Instruction Name\":\"Pdcbt\",\"Args\":[%a,%a]}" p_int n p_ireg ir1 + | Pdcbtst (n,ir1) -> fprintf oc "{\"Instruction Name\":\"Pdcbtst\",\"Args\":[%a,%a]}" p_int n p_ireg ir1 | Pdivw (ir1,ir2,ir3) -> fprintf oc "{\"Instruction Name\":\"Pdivw\",\"Args\":[%a,%a,%a]}" p_ireg ir1 p_ireg ir2 p_ireg ir3 | Pdivwu (ir1,ir2,ir3) -> fprintf oc "{\"Instruction Name\":\"Pdivwu\",\"Args\":[%a,%a,%a]}" p_ireg ir1 p_ireg ir2 p_ireg ir3 | Peieio -> fprintf oc "{\"Instruction Name\":\"Peieio,\"Args\":[]}" diff --git a/powerpc/Asmexpand.ml b/powerpc/Asmexpand.ml index 5216214b..57765c50 100644 --- a/powerpc/Asmexpand.ml +++ b/powerpc/Asmexpand.ml @@ -428,6 +428,17 @@ let expand_builtin_inline name args res = emit (Pdcbi (GPR0,a1)) | "__builtin_icbi", [BA(IR a1)],_ -> emit (Picbi(GPR0,a1)) + | "__builtin_prefetch" , [BA (IR addr);BA_int rw; BA_int loc],_ -> + if not ((loc >= _0) && (loc < _4)) then + raise (Error "the last argument of __builtin_prefetch must be a constant between 0 and 3"); + if Int.eq rw _0 then begin + emit (Pdcbt (loc,addr)); + end else if Int.eq rw _1 then begin + emit (Pdcbtst (loc,addr)); + end else + raise (Error "the second argument of __builtin_prefetch must be either 0 or 1") + | "__builtin_prefetch" ,_,_ -> + raise (Error "the second and third argument of __builtin_prefetch must be a constant") (* Special registers *) | "__builtin_get_spr", [BA_int n], BR(IR res) -> emit (Pmfspr(res, n)) diff --git a/powerpc/CBuiltins.ml b/powerpc/CBuiltins.ml index 75dbd23d..701690b2 100644 --- a/powerpc/CBuiltins.ml +++ b/powerpc/CBuiltins.ml @@ -94,6 +94,8 @@ let builtins = { (TVoid [],[TPtr(TVoid [], [])],false); "__builtin_icbi", (TVoid [],[TPtr(TVoid [], [])],false); + "__builtin_prefetch", + (TVoid [], [TPtr (TVoid [],[]);TInt (IInt, []);TInt (IInt,[])],false); (* Access to special registers *) "__builtin_get_spr", (TInt(IUInt, []), [TInt(IInt, [])], false); diff --git a/powerpc/Machregs.v b/powerpc/Machregs.v index b9af652a..62a4a0a5 100644 --- a/powerpc/Machregs.v +++ b/powerpc/Machregs.v @@ -206,6 +206,7 @@ Definition two_address_op (op: operation) : bool := Definition builtin_get_spr := ident_of_string "__builtin_get_spr". Definition builtin_set_spr := ident_of_string "__builtin_set_spr". +Definition builtin_prefetch := ident_of_string "__builtin_prefetch". Definition builtin_constraints (ef: external_function) : list builtin_arg_constraint := @@ -213,6 +214,7 @@ Definition builtin_constraints (ef: external_function) : | EF_builtin id sg => if ident_eq id builtin_get_spr then OK_const :: nil else if ident_eq id builtin_set_spr then OK_const :: OK_default :: nil + else if ident_eq id builtin_prefetch then OK_addrany :: OK_const :: OK_const :: nil else nil | EF_vload _ => OK_addrany :: nil | EF_vstore _ => OK_addrany :: OK_default :: nil diff --git a/powerpc/TargetPrinter.ml b/powerpc/TargetPrinter.ml index ced26783..b0f296ef 100644 --- a/powerpc/TargetPrinter.ml +++ b/powerpc/TargetPrinter.ml @@ -462,6 +462,10 @@ module Target (System : SYSTEM):TARGET = fprintf oc " dcbf %a, %a\n" ireg r1 ireg r2 | Pdcbi (r1,r2) -> fprintf oc " dcbi %a, %a\n" ireg r1 ireg r2 + | Pdcbt (c,r1) -> + fprintf oc " dcbt %a, %a, %s\n" ireg GPR0 ireg r1 (Z.to_string c) + | Pdcbtst (c,r1) -> + fprintf oc " dcbtst %a, %a, %s\n" ireg GPR0 ireg r1 (Z.to_string c) | Pdivw(r1, r2, r3) -> fprintf oc " divw %a, %a, %a\n" ireg r1 ireg r2 ireg r3 | Pdivwu(r1, r2, r3) -> |