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-rw-r--r--Makefile17
1 files changed, 13 insertions, 4 deletions
diff --git a/Makefile b/Makefile
index baccc9ab..adbfb661 100644
--- a/Makefile
+++ b/Makefile
@@ -23,11 +23,11 @@ endif
BACKENDLIB?=Asmgenproof0.v Asmgenproof1.v
-DIRS=lib lib/Impure common $(ARCHDIRS) backend cfrontend driver \
+DIRS=lib lib/Impure common $(ARCHDIRS) scheduling backend cfrontend driver \
flocq/Core flocq/Prop flocq/Calc flocq/IEEE754 \
exportclight MenhirLib cparser
-RECDIRS=lib common $(ARCHDIRS) backend cfrontend driver flocq exportclight \
+RECDIRS=lib common $(ARCHDIRS) scheduling backend cfrontend driver flocq exportclight \
MenhirLib cparser
COQINCLUDES=$(foreach d, $(RECDIRS), -R $(d) $(subst /,.,compcert.$(d)))
@@ -60,7 +60,9 @@ VLIB=Axioms.v Coqlib.v Intv.v Maps.v Heaps.v Lattice.v Ordered.v \
HashedSet.v \
Iteration.v Zbits.v Integers.v Archi.v IEEE754_extra.v Floats.v \
Parmov.v UnionFind.v Wfsimpl.v \
- Postorder.v FSetAVLplus.v IntvSets.v Decidableplus.v BoolEqual.v
+ Postorder.v FSetAVLplus.v IntvSets.v Decidableplus.v BoolEqual.v \
+ ImpConfig.v ImpExtern.v ImpIO.v ImpMonads.v \
+ ImpCore.v ImpHCons.v ImpLoops.v ImpPrelude.v
# Parts common to the front-ends and the back-end (in common/)
@@ -111,6 +113,13 @@ BACKEND=\
Asm.v Asmgen.v Asmgenproof.v Asmaux.v \
$(BACKENDLIB)
+SCHEDULING= \
+ RTLpathLivegenproof.v RTLpathSE_impl_junk.v \
+ RTLpathLivegen.v RTLpathSE_impl.v \
+ RTLpathproof.v RTLpathSE_theory.v \
+ RTLpathSchedulerproof.v RTLpath.v \
+ RTLpathScheduler.v
+
# C front-end modules (in cfrontend/)
CFRONTEND=Ctypes.v Cop.v Csyntax.v Csem.v Ctyping.v Cstrategy.v Cexec.v \
@@ -136,7 +145,7 @@ DRIVER=Compopts.v Compiler.v Complements.v
# All source files
-FILES=$(VLIB) $(COMMON) $(BACKEND) $(CFRONTEND) $(DRIVER) $(FLOCQ) \
+FILES=$(VLIB) $(COMMON) $(BACKEND) $(SCHEDULING) $(CFRONTEND) $(DRIVER) $(FLOCQ) \
$(MENHIRLIB) $(PARSER)
# Generated source files