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-rw-r--r--kvx/Asmvliw.v18
1 files changed, 11 insertions, 7 deletions
diff --git a/kvx/Asmvliw.v b/kvx/Asmvliw.v
index aa2e0885..45b230e6 100644
--- a/kvx/Asmvliw.v
+++ b/kvx/Asmvliw.v
@@ -313,7 +313,11 @@ Inductive cf_instruction : Type :=
.
(** *** Loads *)
-Definition concrete_default_notrap_load_value (chunk : memory_chunk) :=
+
+(* What follows was the original spec, but is subtly incorrect.
+ Our definition of the assembly-level memory model is already an abstraction of the real world.
+ In particular, we consider that a load is incorrect when it points outside of CompCert's visible memory, whereas this memory could be correct at the assembly level.
+ This means that CompCert would believe an incorrect load would yield 0 whereas it would yield another value.
match chunk with
| Mint8signed | Mint8unsigned | Mint16signed | Mint16unsigned
| Mint32 => Vint Int.zero
@@ -321,7 +325,7 @@ Definition concrete_default_notrap_load_value (chunk : memory_chunk) :=
| Many32 | Many64 => Vundef
| Mfloat32 => Vsingle Float32.zero
| Mfloat64 => Vfloat Float.zero
- end.
+ end. *)
Inductive load_name : Type :=
| Plb (**r load byte *)
@@ -1169,16 +1173,16 @@ Definition eval_offset (ofs: offset) : res ptrofs := OK ofs.
(** *** load/store instructions *)
-Definition parexec_incorrect_load trap chunk d rsw mw :=
+Definition parexec_incorrect_load trap d rsw mw :=
match trap with
| TRAP => Stuck
- | NOTRAP => Next (rsw#d <- (concrete_default_notrap_load_value chunk)) mw
+ | NOTRAP => Next (rsw#d <- Vundef) mw
end.
Definition parexec_load_offset (trap: trapping_mode) (chunk: memory_chunk) (rsr rsw: regset) (mr mw: mem) (d a: ireg) (ofs: offset) :=
match (eval_offset ofs) with
| OK ptr => match Mem.loadv chunk mr (Val.offset_ptr (rsr a) ptr) with
- | None => parexec_incorrect_load trap chunk d rsw mw
+ | None => parexec_incorrect_load trap d rsw mw
| Some v => Next (rsw#d <- v) mw
end
| _ => Stuck
@@ -1225,13 +1229,13 @@ Definition parexec_load_o_offset (rsr rsw: regset) (mr mw: mem) (d : gpreg_o) (a
Definition parexec_load_reg (trap: trapping_mode) (chunk: memory_chunk) (rsr rsw: regset) (mr mw: mem) (d a ro: ireg) :=
match Mem.loadv chunk mr (Val.addl (rsr a) (rsr ro)) with
- | None => parexec_incorrect_load trap chunk d rsw mw
+ | None => parexec_incorrect_load trap d rsw mw
| Some v => Next (rsw#d <- v) mw
end.
Definition parexec_load_regxs (trap: trapping_mode) (chunk: memory_chunk) (rsr rsw: regset) (mr mw: mem) (d a ro: ireg) :=
match Mem.loadv chunk mr (Val.addl (rsr a) (Val.shll (rsr ro) (scale_of_chunk chunk))) with
- | None => parexec_incorrect_load trap chunk d rsw mw
+ | None => parexec_incorrect_load trap d rsw mw
| Some v => Next (rsw#d <- v) mw
end.