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-rw-r--r--scheduling/InstructionScheduler.ml79
1 files changed, 77 insertions, 2 deletions
diff --git a/scheduling/InstructionScheduler.ml b/scheduling/InstructionScheduler.ml
index 976037bd..08164293 100644
--- a/scheduling/InstructionScheduler.ml
+++ b/scheduling/InstructionScheduler.ml
@@ -34,6 +34,7 @@ type problem = {
max_latency : int;
resource_bounds : int array;
live_regs_entry : Registers.Regset.t;
+ typing : RTLtyping.regenv;
instruction_usages : int array array;
latency_constraints : latency_constraint list;
};;
@@ -258,8 +259,8 @@ let priority_list_scheduler (order : list_scheduler_order)
assert(!time >= 0);
!time
with Exit -> -1
-
in
+
let advance_time() =
begin
(if !current_time < max_time-1
@@ -268,7 +269,8 @@ let priority_list_scheduler (order : list_scheduler_order)
Array.blit problem.resource_bounds 0 current_resources 0
(Array.length current_resources);
ready.(!current_time + 1) <-
- InstrSet.union (ready.(!current_time)) (ready.(!current_time + 1));
+ InstrSet.union (ready.(!current_time))
+ (ready.(!current_time + 1));
ready.(!current_time) <- InstrSet.empty;
end);
incr current_time
@@ -335,6 +337,75 @@ let list_scheduler = priority_list_scheduler CRITICAL_PATH_ORDER;;
(* dummy code for placating ocaml's warnings *)
let _ = fun x -> priority_list_scheduler INSTRUCTION_ORDER x;;
+
+(* A scheduler sensitive to register pressure *)
+let reg_pres_scheduler (problem : problem) : solution option =
+ let nr_instructions = get_nr_instructions problem in
+ let successors = get_successors problem
+ and predecessors = get_predecessors problem
+ and times = Array.make (nr_instructions+1) (-1) in
+ let live_regs_entry = problem.live_regs_entry in
+
+ let available_regs = Array.copy Machregsaux.nr_regs in
+
+ List.iter (fun r -> let classe = Machregsaux.class_of_type
+ (problem.typing r) in
+ available_regs.(classe)
+ <- available_regs.(classe) - 1)
+ (Registers.Regset.elements live_regs_entry);
+
+ let nr_types_regs = Array.length available_regs in
+
+ (* wait di we have access to instructions here? No, we have to add
+ al this to constraints *)
+ (* let pressures =
+ * Array.init (nr_instructions) (fun i ->
+ * Array.init (nr_types_regs) (fun t ->
+ * match i with
+ * | Inop -> 0
+ * | Iop (_, args, dest, _)
+ * | Iload(_, _, _, args, dest, _) ->
+ * if
+ * )) *)
+
+ let priorities = critical_paths successors in
+
+ let module InstrSetCSP =
+ Set.Make (struct
+ type t=int
+ let compare x y =
+ match priorities.(y) - priorities.(x) with
+ | 0 -> x - y
+ | z -> z
+ end) in
+
+ (* TODO: find a way to efficiently find an instruction which
+ decreases register pressure *)
+ (* idea: *)
+ (* let module InstrSetCSR =
+ * Set.Make (struct
+ * type t = int
+ * let compare x y =
+ * match pressures.(y) - pressures.(x) with
+ * | 0 -> (match priorities.(y) - priorities.(x) with
+ * | 0 -> x - y
+ * | z -> z)
+ * | z -> z
+ * end) in *)
+ (* where pressure.(x) is the delta of register pressure for
+ instruction x. Pb: different register types. Need to think about
+ it. Have one module for each register type, that's used when this
+ particular type reach a high pressure? *)
+
+ let max_time = bound_max_time problem in
+ let ready = Array.make max_time InstrSetCSP.empty in
+
+ (* silence warning, enable compilation while working *)
+ let _ = successors, predecessors, times, ready, nr_types_regs in
+ (* PLACEHOLDER *)
+ None
+
+
type bundle = int list;;
let rec extract_deps_to index = function
@@ -440,6 +511,10 @@ let reverse_problem problem =
max_latency = problem.max_latency;
resource_bounds = problem.resource_bounds;
live_regs_entry = Registers.Regset.empty; (* PLACEHOLDER *)
+ (* Not needed for the revlist sched, and for now we wont bother
+ with creating a reverse scheduler aware of reg press *)
+
+ typing = problem.typing;
instruction_usages = Array.init (nr_instructions + 1)
(fun i ->
if i=0