diff options
Diffstat (limited to 'scheduling/InstructionScheduler.mli')
| -rw-r--r-- | scheduling/InstructionScheduler.mli | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/scheduling/InstructionScheduler.mli b/scheduling/InstructionScheduler.mli index f53dc0ef..8dcc4ef5 100644 --- a/scheduling/InstructionScheduler.mli +++ b/scheduling/InstructionScheduler.mli @@ -26,6 +26,9 @@ type problem = { live_regs_entry : Registers.Regset.t; (** The set of live pseudo-registers at entry. *) + typing : RTLtyping.regenv; + (** Register type map. *) + instruction_usages: int array array; (** At index {i i} the vector of resources used by instruction number {i i}. It must be the same length as [resource_bounds] *) @@ -71,6 +74,10 @@ Once a clock tick is full go to the next. @return [Some solution] when a solution is found, [None] if not. *) val list_scheduler : problem -> solution option +(** WIP : Same as list_scheduler, but schedules instructions which decrease +register pressure when it gets too high. *) +val reg_pres_scheduler : problem -> solution option + (** Schedule the problem using the order of instructions without any reordering *) val greedy_scheduler : problem -> solution option |