| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Adding info field for branching in RTL, LTL, XTL and all associated passes | Cyril SIX | 2020-03-11 | 1 | -1/+1 |
| * | ONE "admitted" and things compile | David Monniaux | 2019-09-06 | 1 | -1/+1 |
| * | Introduce register pairs to describe calling conventions more precisely | Xavier Leroy | 2016-05-17 | 1 | -0/+1 |
| * | Refactoring of builtins and annotations in the back-end. | Xavier Leroy | 2015-08-21 | 1 | -2/+1 |
| * | Updated the Caml part. Added some more tests in annot1.c. | Xavier Leroy | 2015-03-27 | 1 | -0/+1 |
| * | In Regalloc, dead code elimination, don't eliminate move operations | xleroy | 2014-02-23 | 1 | -0/+4 |
| * | Change interface of Kildall solvers to avoid precomputing the map pc -> list ... | xleroy | 2013-08-12 | 1 | -1/+0 |
| * | Big merge of the newregalloc-int64 branch. Lots of changes in two directions: | xleroy | 2013-04-20 | 1 | -0/+100 |
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index : compcert-kvx | |
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