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* Merge remote-tracking branch 'origin/mppa-work-upstream-merge' into mppa-workCyril SIX2019-09-031-0/+9
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| * fmaDavid Monniaux2019-08-301-0/+4
| * add finvw ; not yet generatedDavid Monniaux2019-08-301-0/+1
| * fmin/fmax/fminf/fmaxf non bien testésDavid Monniaux2019-08-291-0/+4
* | (#156) - Un peu de cleaning et de docCyril SIX2019-07-301-20/+15
* | (#139) - Quelques renommagesCyril SIX2019-07-301-5/+5
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* (#107) Rename "forward_simu" into "bisimu"Cyril SIX2019-07-171-27/+27
* maj forward_simu_par_wio_bblock_aux en forward_simu_par_wioSylvain Boulmé2019-06-231-12/+10
* Merge branch 'mppa-work' into mppa-abstractbb-devSylvain Boulmé2019-06-081-1/+17
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| * added immediate cmoveDavid Monniaux2019-06-041-0/+4
| * begin generating Prevsub etc. from Oxxx to PxxxDavid Monniaux2019-05-111-6/+6
| * new instructions at asm levelDavid Monniaux2019-05-101-1/+13
* | simpler definition of reduceSylvain Boulmé2019-05-281-4/+15
* | extending bblock_simu_test with rewritingSylvain Boulmé2019-05-261-35/+28
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* generalize bblock_equiv into bblock_simu (abstract_bb)Sylvain Boulmé2019-05-071-22/+17
* generalize bblock_equiv into bblock_simuSylvain Boulmé2019-05-071-16/+16
* simplification semantique+preuve des load_q+load_oSylvain Boulmé2019-05-061-255/+62
* mergedDavid Monniaux2019-05-041-4/+3
* Merge branch 'mppa-peephole' of gricad-gitlab.univ-grenoble-alpes.fr:sixcy/Co...David Monniaux2019-05-041-5/+2
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| * legere simplification de preuveSylvain Boulmé2019-05-041-70/+26
* | big proofs for so / loDavid Monniaux2019-05-041-3/+199
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* Lq finished ?David Monniaux2019-05-031-15/+16
* begin add PlqDavid Monniaux2019-05-031-2/+58
* use sq to save pairs of registersDavid Monniaux2019-05-031-3/+16
* ça avanceDavid Monniaux2019-05-031-0/+27
* Merge remote-tracking branch 'origin/mppa-work' into mppa-peepholeDavid Monniaux2019-05-031-4/+5
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| * rm Ofslow (résidu du Risc-V, inutilisé et complique les preuves)David Monniaux2019-05-031-4/+5
* | getting stuck need to move offsetsDavid Monniaux2019-05-031-3/+8
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* does not yet work, arity mismatchDavid Monniaux2019-05-011-0/+1
* it compilesDavid Monniaux2019-05-011-0/+20
* begin load.xsDavid Monniaux2019-05-011-0/+20
* removed fake ops for int32 -> doubleDavid Monniaux2019-04-291-2/+0
* Srsd / SrswDavid Monniaux2019-04-291-0/+4
* begin add bitfield insertionDavid Monniaux2019-04-271-2/+18
* start of extfzl/extfslDavid Monniaux2019-04-251-0/+2
* progressDavid Monniaux2019-04-251-0/+1
* begin bitfieldsDavid Monniaux2019-04-241-0/+1
* more robust pattern-matching in *op_eqSylvain Boulmé2019-04-111-8/+10
* refactor for #92Sylvain Boulmé2019-04-111-785/+305
* achieve issue #89 ?Sylvain Boulmé2019-04-101-185/+47
* Merge remote-tracking branch 'origin/mppa-work' into mppa-refactorCyril SIX2019-04-081-0/+2
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| * select cmpuDavid Monniaux2019-04-051-0/+1
| * Merge remote-tracking branch 'origin/mppa-work' into mppa-ternaryDavid Monniaux2019-04-041-350/+185
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| * \ Merge remote-tracking branch 'origin/mppa-work' into mppa-ternaryDavid Monniaux2019-04-031-262/+432
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| * \ \ merge VLIW proofsDavid Monniaux2019-03-281-4/+518
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| * | | | progress on cmoveDavid Monniaux2019-03-251-0/+1
* | | | | Merge remote-tracking branch 'origin/mppa-refactor-reviewed' into mppa-refactorCyril SIX2019-04-081-17/+17
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| * | | | | relecture sylvainSylvain Boulmé2019-04-051-17/+17
* | | | | | #91 Removed completely the duplicated semantics in AsmblockCyril SIX2019-04-051-34/+34
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* | | | / #90 Asmvliw/Asmblock refactoring attemptCyril SIX2019-04-051-7/+7
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